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quicklogic: Move pp3 tests one level down

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This commit is contained in:
Martin Povišer 2023-10-09 13:13:42 +02:00
parent e43810e13f
commit 6672b6c1b3
11 changed files with 11 additions and 11 deletions
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2
tests/arch/quicklogic/add_sub.ys → tests/arch/quicklogic/pp3/add_sub.ys
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@ -1,4 +1,4 @@
read_verilog ../common/add_sub.v
read_verilog ../../common/add_sub.v
hierarchy -top top
equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

2
tests/arch/quicklogic/adffs.ys → tests/arch/quicklogic/pp3/adffs.ys
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@ -1,4 +1,4 @@
read_verilog ../common/adffs.v
read_verilog ../../common/adffs.v
design -save read
hierarchy -top adff

2
tests/arch/quicklogic/counter.ys → tests/arch/quicklogic/pp3/counter.ys
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@ -1,4 +1,4 @@
read_verilog ../common/counter.v
read_verilog ../../common/counter.v
hierarchy -top top
proc
flatten

2
tests/arch/quicklogic/dffs.ys → tests/arch/quicklogic/pp3/dffs.ys
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@ -1,4 +1,4 @@
read_verilog ../common/dffs.v
read_verilog ../../common/dffs.v
rename dff my_dff # Work around conflicting module names between test and vendor cells
rename dffe my_dffe
design -save read

2
tests/arch/quicklogic/fsm.ys → tests/arch/quicklogic/pp3/fsm.ys
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@ -1,4 +1,4 @@
read_verilog ../common/fsm.v
read_verilog ../../common/fsm.v
hierarchy -top fsm
proc
flatten

2
tests/arch/quicklogic/latches.ys → tests/arch/quicklogic/pp3/latches.ys
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@ -1,4 +1,4 @@
read_verilog ../common/latches.v
read_verilog ../../common/latches.v
design -save read
hierarchy -top latchp

2
tests/arch/quicklogic/logic.ys → tests/arch/quicklogic/pp3/logic.ys
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@ -1,4 +1,4 @@
read_verilog ../common/logic.v
read_verilog ../../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check

2
tests/arch/quicklogic/mux.ys → tests/arch/quicklogic/pp3/mux.ys
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@ -1,4 +1,4 @@
read_verilog ../common/mux.v
read_verilog ../../common/mux.v
design -save read
hierarchy -top mux2

2
tests/arch/quicklogic/run-test.sh → tests/arch/quicklogic/pp3/run-test.sh
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@ -1,4 +1,4 @@
#!/usr/bin/env bash
set -eu
source ../../gen-tests-makefile.sh
source ../../../gen-tests-makefile.sh
run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"

2
tests/arch/quicklogic/tribuf.ys → tests/arch/quicklogic/pp3/tribuf.ys
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@ -1,4 +1,4 @@
read_verilog ../common/tribuf.v
read_verilog ../../common/tribuf.v
hierarchy -top tristate
proc
tribuf