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xilinx_dsp: Initial DSP48A/DSP48A1 support.

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This commit is contained in:
Marcin Kościelnicki 2019-12-22 20:43:39 +01:00
parent aa1adb0f1e
commit 666c6128a9
10 changed files with 921 additions and 14 deletions
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3
tests/arch/xilinx/macc.sh
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@ -1,3 +1,6 @@
../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
vvp -N ./test_macc
../../../yosys -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
vvp -N ./test_macc

12
tests/arch/xilinx/mul.ys
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@ -7,3 +7,15 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D
design -reset
read_verilog ../common/mul.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:DSP48A1
select -assert-none t:DSP48A1 %% t:* %D

14
tests/arch/xilinx/mul_unsigned.ys
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@ -9,3 +9,17 @@ select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 30 t:FDRE
select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D
design -reset
read_verilog mul_unsigned.v
hierarchy -top mul_unsigned
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48A1
select -assert-count 30 t:FDRE
select -assert-none t:DSP48A1 t:FDRE t:BUFG %% t:* %D