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xilinx_dsp: Initial DSP48A/DSP48A1 support.
This commit is contained in:
Marcin Kościelnicki
parent
aa1adb0f1e
commit
666c6128a9
10 changed files with 921 additions and 14 deletions
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@ -26,6 +26,7 @@ USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/xilinx_dsp_pm.h"
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#include "passes/pmgen/xilinx_dsp48a_pm.h"
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#include "passes/pmgen/xilinx_dsp_CREG_pm.h"
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#include "passes/pmgen/xilinx_dsp_cascade_pm.h"
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@ -487,6 +488,190 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
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pm.blacklist(cell);
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}
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void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp48a_pack;
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log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", log_id(pm.module), log_id(st.dsp));
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log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
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log_debug("ffA1: %s %s %s\n", log_id(st.ffA1, "--"), log_id(st.ffA1cemux, "--"), log_id(st.ffA1rstmux, "--"));
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log_debug("ffA0: %s %s %s\n", log_id(st.ffA0, "--"), log_id(st.ffA0cemux, "--"), log_id(st.ffA0rstmux, "--"));
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log_debug("ffB1: %s %s %s\n", log_id(st.ffB1, "--"), log_id(st.ffB1cemux, "--"), log_id(st.ffB1rstmux, "--"));
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log_debug("ffB0: %s %s %s\n", log_id(st.ffB0, "--"), log_id(st.ffB0cemux, "--"), log_id(st.ffB0rstmux, "--"));
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log_debug("ffD: %s %s %s\n", log_id(st.ffD, "--"), log_id(st.ffDcemux, "--"), log_id(st.ffDrstmux, "--"));
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log_debug("dsp: %s\n", log_id(st.dsp, "--"));
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log_debug("ffM: %s %s %s\n", log_id(st.ffM, "--"), log_id(st.ffMcemux, "--"), log_id(st.ffMrstmux, "--"));
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log_debug("postAdd: %s\n", log_id(st.postAdd, "--"));
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log_debug("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log_debug("ffP: %s %s %s\n", log_id(st.ffP, "--"), log_id(st.ffPcemux, "--"), log_id(st.ffPrstmux, "--"));
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Cell *cell = st.dsp;
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SigSpec &opmode = cell->connections_.at(ID(OPMODE));
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if (st.preAdd) {
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log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
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bool D_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool();
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bool B_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool();
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st.sigB.extend_u0(18, B_SIGNED);
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st.sigD.extend_u0(18, D_SIGNED);
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cell->setPort(ID(B), st.sigB);
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cell->setPort(ID(D), st.sigD);
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opmode[4] = State::S1;
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if (st.preAdd->type == ID($add))
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opmode[6] = State::S0;
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else if (st.preAdd->type == ID($sub))
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opmode[6] = State::S1;
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else
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log_assert(!"strange pre-adder type");
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pm.autoremove(st.preAdd);
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}
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if (st.postAdd) {
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log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
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if (st.postAddMux) {
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log_assert(st.ffP);
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opmode[2] = st.postAddMux->getPort(ID(S));
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pm.autoremove(st.postAddMux);
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}
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else if (st.ffP && st.sigC == st.sigP)
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opmode[2] = State::S0;
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else
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opmode[2] = State::S1;
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opmode[3] = State::S1;
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if (opmode[2] != State::S0) {
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if (st.postAddMuxAB == ID(A))
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st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool());
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else
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st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool());
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cell->setPort(ID(C), st.sigC);
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}
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pm.autoremove(st.postAdd);
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}
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if (st.clock != SigBit())
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{
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cell->setPort(ID(CLK), st.clock);
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auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
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SigSpec D = ff->getPort(ID(D));
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SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
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if (!A.empty())
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A.replace(Q, D);
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if (rstmux) {
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SigSpec Y = rstmux->getPort(ID(Y));
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SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
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if (!A.empty())
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A.replace(Y, AB);
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if (rstport != IdString()) {
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SigSpec S = rstmux->getPort(ID(S));
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cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
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}
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}
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else if (rstport != IdString())
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cell->setPort(rstport, State::S0);
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if (cemux) {
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SigSpec Y = cemux->getPort(ID(Y));
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SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
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SigSpec S = cemux->getPort(ID(S));
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if (!A.empty())
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A.replace(Y, BA);
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cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort(ceport, State::S1);
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for (auto c : Q.chunks()) {
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auto it = c.wire->attributes.find(ID(init));
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if (it == c.wire->attributes.end())
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continue;
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for (int i = c.offset; i < c.offset+c.width; i++) {
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log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
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it->second[i] = State::Sx;
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}
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}
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};
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if (st.ffA0 || st.ffA1) {
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SigSpec A = cell->getPort(ID(A));
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if (st.ffA1) {
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f(A, st.ffA1, st.ffA1cemux, st.ffAcepol, ID(CEA), st.ffA1rstmux, st.ffArstpol, ID(RSTA));
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cell->setParam(ID(A1REG), 1);
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}
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if (st.ffA0) {
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f(A, st.ffA0, st.ffA0cemux, st.ffAcepol, ID(CEA), st.ffA0rstmux, st.ffArstpol, ID(RSTA));
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cell->setParam(ID(A0REG), 1);
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}
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pm.add_siguser(A, cell);
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cell->setPort(ID(A), A);
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}
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if (st.ffB0 || st.ffB1) {
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SigSpec B = cell->getPort(ID(B));
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if (st.ffB1) {
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f(B, st.ffB1, st.ffB1cemux, st.ffBcepol, ID(CEB), st.ffB1rstmux, st.ffBrstpol, ID(RSTB));
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cell->setParam(ID(B1REG), 1);
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}
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if (st.ffB0) {
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f(B, st.ffB0, st.ffB0cemux, st.ffBcepol, ID(CEB), st.ffB0rstmux, st.ffBrstpol, ID(RSTB));
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cell->setParam(ID(B0REG), 1);
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}
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pm.add_siguser(B, cell);
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cell->setPort(ID(B), B);
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}
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if (st.ffD) {
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SigSpec D = cell->getPort(ID(D));
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f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
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pm.add_siguser(D, cell);
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cell->setPort(ID(D), D);
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cell->setParam(ID(DREG), 1);
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}
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if (st.ffM) {
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SigSpec M; // unused
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f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
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st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
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cell->setParam(ID(MREG), State::S1);
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}
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if (st.ffP) {
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SigSpec P; // unused
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f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
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st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
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cell->setParam(ID(PREG), State::S1);
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}
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log(" clock: %s (%s)", log_signal(st.clock), "posedge");
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if (st.ffA0)
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log(" ffA0:%s", log_id(st.ffA0));
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if (st.ffA1)
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log(" ffA1:%s", log_id(st.ffA1));
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if (st.ffB0)
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log(" ffB0:%s", log_id(st.ffB0));
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if (st.ffB1)
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log(" ffB1:%s", log_id(st.ffB1));
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if (st.ffD)
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log(" ffD:%s", log_id(st.ffD));
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if (st.ffM)
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log(" ffM:%s", log_id(st.ffM));
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if (st.ffP)
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log(" ffP:%s", log_id(st.ffP));
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}
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log("\n");
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SigSpec P = st.sigP;
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if (GetSize(P) < 48)
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P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
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cell->setPort(ID(P), P);
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pm.blacklist(cell);
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}
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void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp_packC;
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@ -592,33 +777,48 @@ struct XilinxDspPass : public Pass {
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log("P output implementing the operation \"(P >= <power-of-2>)\" will be transformed\n");
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log("into using the DSP48E1's pattern detector feature for overflow detection.\n");
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log("\n");
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log(" -family {xcup|xcu|xc7|xc6v|xc5v|xc4v|xc6s|xc3sda}\n");
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log(" select the family to target\n");
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log(" default: xc7\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing XILINX_DSP pass (pack resources into DSPs).\n");
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std::string family = "xc7";
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
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family = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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// Don't bother distinguishing between those.
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if (family == "xc6v")
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family = "xc7";
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if (family == "xcup")
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family = "xcu";
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for (auto module : design->selected_modules()) {
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// Experimental feature: pack $add/$sub cells with
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// (* use_dsp48="simd" *) into DSP48E1's using its
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// SIMD feature
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xilinx_simd_pack(module, module->selected_cells());
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if (family == "xc7")
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xilinx_simd_pack(module, module->selected_cells());
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// Match for all features ([ABDMP][12]?REG, pre-adder,
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// post-adder, pattern detector, etc.) except for CREG
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{
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if (family == "xc7") {
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xilinx_dsp_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
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} else if (family == "xc6s" || family == "xc3sda") {
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xilinx_dsp48a_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp48a_pack(xilinx_dsp48a_pack);
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}
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// Separating out CREG packing is necessary since there
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// is no guarantee that the cell ordering corresponds
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