mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 01:24:10 +00:00
Code Activity

Remove Xilinx test

Browse source
This commit is contained in:
Eddie Hung 2019-08-22 16:18:07 -07:00
parent 53fed4f7e9
commit 66607845ec
1 changed files with 0 additions and 34 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

34
tests/various/shregmap.ys
View file

@ -31,37 +31,3 @@ sat -verify -prove-asserts -show-ports -seq 5 miter
#design -load gate
#stat
##########
design -load read
design -copy-to model $__XILINX_SHREG_
hierarchy -top shregmap_variable_test
prep
design -save gold
simplemap t:$dff t:$dffe
shregmap -tech xilinx
#stat
# show -width
# write_verilog -noexpr -norename
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__XILINX_SHREG_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
# design -load gold
# stat
# design -load gate
# stat