3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 09:55:20 +00:00

Merge branch 'main' into synth-flatten

This commit is contained in:
Peter Gadfort 2025-01-20 10:24:38 -07:00
commit 66545caa1b
6 changed files with 55 additions and 13 deletions

View file

@ -8,7 +8,7 @@ runs:
shell: bash shell: bash
run: | run: |
sudo apt-get update sudo apt-get update
sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev libbz2-dev
- name: Install macOS Dependencies - name: Install macOS Dependencies
if: runner.os == 'macOS' if: runner.os == 'macOS'

View file

@ -30,18 +30,15 @@ jobs:
- ubuntu-latest - ubuntu-latest
compiler: compiler:
# oldest supported # oldest supported
- 'clang-14' - 'clang-10'
- 'gcc-10' - 'gcc-10'
# newest, make sure to update maximum standard step to match # newest, make sure to update maximum standard step to match
- 'clang-18' - 'clang-19'
- 'gcc-13' - 'gcc-13'
include: include:
# macOS # macOS
- os: macos-13 - os: macos-13
compiler: 'clang' compiler: 'clang'
# oldest clang not available on ubuntu-latest
- os: ubuntu-20.04
compiler: 'clang-10'
fail-fast: false fail-fast: false
steps: steps:
- name: Checkout Yosys - name: Checkout Yosys
@ -72,7 +69,7 @@ jobs:
# maximum standard, only on newest compilers # maximum standard, only on newest compilers
- name: Build C++20 - name: Build C++20
if: ${{ matrix.compiler == 'clang-18' || matrix.compiler == 'gcc-13' }} if: ${{ matrix.compiler == 'clang-19' || matrix.compiler == 'gcc-13' }}
shell: bash shell: bash
run: | run: |
make config-$CC_SHORT make config-$CC_SHORT

View file

@ -11,6 +11,29 @@ yosys_ver = "0.48"
# select HTML theme # select HTML theme
html_theme = 'furo-ys' html_theme = 'furo-ys'
html_css_files = ['custom.css'] html_css_files = ['custom.css']
html_theme_options: dict[str] = {
"source_repository": "https://github.com/YosysHQ/yosys/",
"source_branch": "main",
"source_directory": "docs/source/",
}
# try to fix the readthedocs detection
html_context: dict[str] = {
"READTHEDOCS": True,
"display_github": True,
"github_user": "YosysHQ",
"github_repo": "yosys",
"slug": "yosys",
}
# override source_branch if not main
git_slug = os.getenv("READTHEDOCS_VERSION_NAME")
if git_slug not in [None, "latest", "stable"]:
html_theme_options["source_branch"] = git_slug
# edit only works on branches, not tags
if os.getenv("READTHEDOCS_VERSION_TYPE", "branch") != "branch":
html_theme_options["top_of_page_buttons"] = ["view"]
# These folders are copied to the documentation's HTML output # These folders are copied to the documentation's HTML output
html_static_path = ['_static', "_images"] html_static_path = ['_static', "_images"]

View file

@ -1464,7 +1464,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log("Importing module %s.\n", RTLIL::id2cstr(module->name)); log("Importing module %s.\n", RTLIL::id2cstr(module->name));
} }
import_attributes(module->attributes, nl, nl); import_attributes(module->attributes, nl, nl);
module->set_string_attribute(ID::hdlname, nl->CellBaseName()); if (module->name.isPublic())
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name()); module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
if (nl->IsFromVhdl()) { if (nl->IsFromVhdl()) {

View file

@ -337,12 +337,14 @@ template<typename O>
std::vector<IdString> parse_hdlname(const O* object) std::vector<IdString> parse_hdlname(const O* object)
{ {
std::vector<IdString> path; std::vector<IdString> path;
if (!object->name.isPublic())
return path;
for (auto const &item : object->get_hdlname_attribute()) for (auto const &item : object->get_hdlname_attribute())
path.push_back("\\" + item); path.push_back("\\" + item);
if (path.empty()) if (path.empty() && object->name.isPublic())
path.push_back(object->name); path.push_back(object->name);
if (!path.empty() && !(object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract"))) {
path.pop_back();
path.push_back(object->name);
}
return path; return path;
} }
@ -351,17 +353,22 @@ std::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)
{ {
std::vector<IdString> path; std::vector<IdString> path;
IdString trailing = object->name; IdString trailing = object->name;
if (object->name.isPublic()) { if (object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract")) {
for (auto const &item : object->get_hdlname_attribute()) for (auto const &item : object->get_hdlname_attribute())
path.push_back("\\" + item); path.push_back("\\" + item);
if (!path.empty()) { if (!path.empty()) {
trailing = path.back(); trailing = path.back();
path.pop_back(); path.pop_back();
} }
} else if (object->has_attribute(ID::hdlname)) {
for (auto const &item : object->get_hdlname_attribute())
path.push_back("\\" + item);
if (!path.empty()) {
path.pop_back();
}
} else { } else {
for (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), " ")) for (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), " "))
path.push_back("\\" + item); path.push_back("\\" + item);
} }
return {path, trailing}; return {path, trailing};
} }

View file

@ -377,6 +377,13 @@ static void extract_fsm(RTLIL::Wire *wire)
fsm_cell->setPort(ID::CTRL_OUT, ctrl_out); fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str()); fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
fsm_cell->attributes = wire->attributes; fsm_cell->attributes = wire->attributes;
if(fsm_cell->attributes.count(ID::hdlname)) {
auto hdlname = fsm_cell->get_hdlname_attribute();
hdlname.pop_back();
fsm_cell->set_hdlname_attribute(hdlname);
fsm_cell->set_string_attribute(ID(scopename), fsm_cell->get_string_attribute(ID::hdlname));
fsm_cell->attributes.erase(ID::hdlname);
}
fsm_data.copy_to_cell(fsm_cell); fsm_data.copy_to_cell(fsm_cell);
// rename original state wire // rename original state wire
@ -385,6 +392,13 @@ static void extract_fsm(RTLIL::Wire *wire)
wire->attributes.erase(ID::fsm_encoding); wire->attributes.erase(ID::fsm_encoding);
wire->name = stringf("$fsm$oldstate%s", wire->name.c_str()); wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
module->wires_[wire->name] = wire; module->wires_[wire->name] = wire;
if(wire->attributes.count(ID::hdlname)) {
auto hdlname = wire->get_hdlname_attribute();
hdlname.pop_back();
wire->set_hdlname_attribute(hdlname);
wire->set_string_attribute(ID(scopename), wire->get_string_attribute(ID::hdlname));
wire->attributes.erase(ID::hdlname);
}
// unconnect control outputs from old drivers // unconnect control outputs from old drivers