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flatten: simplify.

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Flattening does not benefit from topologically sorting cells within
a module when processing them.
This commit is contained in:
whitequark 2020-06-03 16:00:40 +00:00
parent 5d2b6d1394
commit 66255dab4e
1 changed files with 0 additions and 35 deletions
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35
passes/techmap/flatten.cc
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@ -260,10 +260,6 @@ struct FlattenWorker
SigMap sigmap(module);
TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->selected_cells())
{
if (!design->has(cell->type))
@ -279,37 +275,6 @@ struct FlattenWorker
continue;
}
for (auto &conn : cell->connections())
{
RTLIL::SigSpec sig = sigmap(conn.second);
sig.remove_const();
if (GetSize(sig) == 0)
continue;
RTLIL::Module *tpl = design->module(cell->type);
RTLIL::Wire *port = tpl->wire(conn.first);
if (port && port->port_input)
cell_to_inbit[cell].insert(sig.begin(), sig.end());
if (port && port->port_output)
for (auto &bit : sig)
outbit_to_cell[bit].insert(cell);
}
cells.node(cell);
}
for (auto &it_right : cell_to_inbit)
for (auto &it_sigbit : it_right.second)
for (auto &it_left : outbit_to_cell[it_sigbit])
cells.edge(it_left, it_right.first);
cells.sort();
for (auto cell : cells.sorted)
{
log_assert(cell == module->cell(cell->name));
RTLIL::Module *tpl = design->module(cell->type);
dict<IdString, RTLIL::Const> parameters(cell->parameters);