From e0c879684f510ae6fd1169c90d137e660c88e6be Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 1 Jan 2020 16:13:14 +0100
Subject: [PATCH 1/2] take skip wire bits into account

---
 passes/techmap/iopadmap.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 47da98b06..531ac2b99 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -234,6 +234,9 @@ struct IopadmapPass : public Pass {
 						SigBit wire_bit(wire, i);
 						Cell *tbuf_cell = nullptr;
 
+						if (skip_wire_bits.count(wire_bit))
+							continue;
+
 						if (tbuf_bits.count(wire_bit))
 							tbuf_cell = tbuf_bits.at(wire_bit);
 

From a1344ec06ead35a3b7933ee93b5757eeff2e5d4a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 1 Jan 2020 16:24:30 +0100
Subject: [PATCH 2/2] Added a test case

---
 tests/arch/xilinx/bug1605.ys | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 tests/arch/xilinx/bug1605.ys

diff --git a/tests/arch/xilinx/bug1605.ys b/tests/arch/xilinx/bug1605.ys
new file mode 100644
index 000000000..4be659860
--- /dev/null
+++ b/tests/arch/xilinx/bug1605.ys
@@ -0,0 +1,19 @@
+read_verilog <<EOT
+module top(inout io);
+    wire in;
+    wire t;
+    wire o;
+
+    IOBUF IOBUF(
+      .I(in),
+      .T(t),
+      .IO(io),
+      .O(o)
+    );
+endmodule
+EOT
+
+synth_xilinx
+cd top
+select -assert-count 1 t:IOBUF
+select -assert-none t:* t:IOBUF %d