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https://github.com/YosysHQ/yosys
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Added mapping of synchronous set/reset to iCE40 flow
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parent
e050467b89
commit
661b647559
3 changed files with 130 additions and 4 deletions
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@ -63,9 +63,9 @@ struct SynthIce40Pass : public Pass {
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log(" synth -run coarse\n");
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log("\n");
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log(" fine:\n");
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log(" opt -fast -full\n");
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log(" opt -fast -mux_undef -undriven -fine\n");
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log(" memory_map\n");
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log(" opt -full\n");
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log(" opt -undriven -fine\n");
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log(" techmap\n");
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log(" opt -fast\n");
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log("\n");
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@ -74,6 +74,7 @@ struct SynthIce40Pass : public Pass {
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log(" techmap -map +/ice40/cells_map.v\n");
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log(" opt_const -mux_undef\n");
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log(" simplemap\n");
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log(" ice40_ffssr\n");
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log(" clean\n");
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log("\n");
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log(" map_luts:\n");
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@ -135,9 +136,9 @@ struct SynthIce40Pass : public Pass {
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if (check_label(active, run_from, run_to, "fine"))
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{
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Pass::call(design, "opt -fast -full");
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Pass::call(design, "opt -fast -mux_undef -undriven -fine");
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Pass::call(design, "memory_map");
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Pass::call(design, "opt -full");
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Pass::call(design, "opt -undriven -fine");
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Pass::call(design, "techmap");
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Pass::call(design, "opt -fast");
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}
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@ -148,6 +149,7 @@ struct SynthIce40Pass : public Pass {
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Pass::call(design, "techmap -map +/ice40/cells_map.v");
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Pass::call(design, "opt_const -mux_undef");
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Pass::call(design, "simplemap");
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Pass::call(design, "ice40_ffssr");
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Pass::call(design, "clean");
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}
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