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Remove DFF and RAMD box info for now

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This commit is contained in:
Eddie Hung 2019-06-21 20:41:14 -07:00
parent 8d18c256f0
commit 65c022c257
2 changed files with 0 additions and 36 deletions
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techlibs/xilinx/cells_sim.v
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@ -281,7 +281,6 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
//(* abc_box_id = 4 /*, lib_whitebox*/ *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
@ -299,7 +298,6 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
//(* abc_box_id = 5 /*, lib_whitebox*/ *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,