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Remove DFF and RAMD box info for now

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This commit is contained in:
Eddie Hung 2019-06-21 20:41:14 -07:00
parent 8d18c256f0
commit 65c022c257
2 changed files with 0 additions and 36 deletions
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34
techlibs/xilinx/abc_xc7.box
View file

@ -26,37 +26,3 @@ CARRY4 3 1 10 8
433 469 - - 494 465 445 - - 157
512 548 292 - 592 540 520 356 - 228
508 528 378 380 580 526 507 398 385 114
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 4 0 15 2
- - - - - - - 124 124 124 124 124 124 - -
124 124 124 124 124 124 - - - - - - 124 - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 5 0 17 2
- - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - -
# Inputs: C CE D R
# Outputs: Q
FDRE 6 0 4 1
- - - -
# Inputs: C CE D S
# Outputs: Q
FDSE 7 0 4 1
- - - -
# Inputs: C CE CLR D
# Outputs: Q
FDCE 8 0 4 1
- - - -
# Inputs: C CE D PRE
# Outputs: Q
FDPE 9 0 4 1
- - - -

2
techlibs/xilinx/cells_sim.v
View file

@ -281,7 +281,6 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
//(* abc_box_id = 4 /*, lib_whitebox*/ *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
@ -299,7 +298,6 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
//(* abc_box_id = 5 /*, lib_whitebox*/ *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,