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Docs: updating to current 'master'

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Pulling for #4133 and removing related TODO.
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Krystine Sherwin 2024-01-22 11:18:07 +13:00
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docs/source/yosys_internals/formats/cell_library.rst
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@ -122,7 +122,7 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port
:verilog:`Y = A >>> B` $sshr :verilog:`Y = A - B` $sub
:verilog:`Y = A && B` $logic_and :verilog:`Y = A * B` $mul
:verilog:`Y = A || B` $logic_or :verilog:`Y = A / B` $div
:verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod
:verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod
:verilog:`Y = A !== B` $nex ``N/A`` $divfloor
:verilog:`Y = A ** B` $pow ``N/A`` $modfoor
======================= ============= ======================= =========
@ -664,6 +664,8 @@ Ports:
``\TRG``
The signals that control when this ``$print`` cell is triggered.
If the width of this port is zero and ``\TRG_ENABLE`` is true, the cell is
triggered during initial evaluation (time zero) only.
``\EN``
Enable signal for the whole cell.