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Docs: updating to current 'master'

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Pulling for #4133 and removing related TODO.
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Krystine Sherwin 2024-01-22 11:18:07 +13:00
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docs/source/getting_started/example_synth.rst
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@ -127,8 +127,6 @@ Our ``addr_gen`` circuit now looks like this:
``addr_gen`` module after :cmd:ref:`hierarchy`
.. TODO:: pending https://github.com/YosysHQ/yosys/pull/4133
Simple operations like ``addr + 1`` and ``addr == MAX_DATA-1`` can be extracted
from our ``always @`` block in :ref:`addr_gen-v`. This gives us the highlighted
``$add`` and ``$eq`` cells we see. But control logic (like the ``if .. else``)