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ast, read_verilog: unify location types, reduce filename copying

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This commit is contained in:
Emil J. Tywoniak 2025-06-18 22:50:46 +02:00
parent 6ac9f79de6
commit 653c002ad0
12 changed files with 715 additions and 693 deletions
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37
frontends/ast/ast.cc
View file

@ -207,7 +207,7 @@ AstNode::AstNode(AstSrcLocType loc, AstNodeType type, std::unique_ptr<AstNode> c
astnodes++; astnodes++;
this->type = type; this->type = type;
loc = loc; location = loc;
is_input = false; is_input = false;
is_output = false; is_output = false;
is_reg = false; is_reg = false;
@ -921,7 +921,7 @@ std::unique_ptr<AstNode> AstNode::mktemp_logic(AstSrcLocType loc, const std::str
{ {
auto wire_owned = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, mkconst_int(loc, range_left, true), mkconst_int(loc, range_right, true))); auto wire_owned = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, mkconst_int(loc, range_left, true), mkconst_int(loc, range_right, true)));
auto* wire = wire_owned.get(); auto* wire = wire_owned.get();
wire->str = stringf("%s%s:%d$%d", name.c_str(), RTLIL::encode_filename(location.filename).c_str(), location.first_line, autoidx++); wire->str = stringf("%s%s:%d$%d", name.c_str(), RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++);
if (nosync) if (nosync)
wire->set_attribute(ID::nosync, AstNode::mkconst_int(loc, 1, false)); wire->set_attribute(ID::nosync, AstNode::mkconst_int(loc, 1, false));
wire->is_signed = is_signed; wire->is_signed = is_signed;
@ -1085,7 +1085,7 @@ RTLIL::Const AstNode::realAsConst(int width)
std::string AstNode::loc_string() const std::string AstNode::loc_string() const
{ {
return stringf("%s:%d.%d-%d.%d", location.filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); return stringf("%s:%d.%d-%d.%d", location.begin.filename->c_str(), location.begin.line, location.begin.column, location.end.line, location.end.column);
} }
void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast) void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
@ -1246,7 +1246,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
ast->children.swap(new_children); ast->children.swap(new_children);
if (ast->attributes.count(ID::blackbox) == 0) { if (ast->attributes.count(ID::blackbox) == 0) {
ast->set_attribute(ID::blackbox, AstNode::mkconst_int(1, false)); ast->set_attribute(ID::blackbox, AstNode::mkconst_int(ast->location, 1, false));
} }
} }
@ -1443,7 +1443,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
if (design->has(child->str)) { if (design->has(child->str)) {
RTLIL::Module *existing_mod = design->module(child->str); RTLIL::Module *existing_mod = design->module(child->str);
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
log_file_error(child->location.filename, child->location.first_line, "Re-definition of module `%s'!\n", child->str.c_str()); log_file_error(*child->location.begin.filename, child->location.begin.line, "Re-definition of module `%s'!\n", child->str.c_str());
} else if (nooverwrite) { } else if (nooverwrite) {
log("Ignoring re-definition of module `%s' at %s.\n", log("Ignoring re-definition of module `%s' at %s.\n",
child->str.c_str(), child->loc_string().c_str()); child->str.c_str(), child->loc_string().c_str());
@ -1526,7 +1526,8 @@ AstNode * AST::find_modport(AstNode *intf, std::string name)
void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport) void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport)
{ {
for (auto w : intfmodule->wires()){ for (auto w : intfmodule->wires()){
auto wire = std::make_unique<AstNode>(AST_WIRE, std::make_unique<AstNode>(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true))); auto loc = module_ast->location;
auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
std::string origname = log_id(w->name); std::string origname = log_id(w->name);
std::string newname = intfname + "." + origname; std::string newname = intfname + "." + origname;
wire->str = newname; wire->str = newname;
@ -1583,11 +1584,12 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
loadconfig(); loadconfig();
auto new_ast = ast->clone(); auto new_ast = ast->clone();
auto loc = ast->location;
for (auto &intf : local_interfaces) { for (auto &intf : local_interfaces) {
std::string intfname = intf.first.str(); std::string intfname = intf.first.str();
RTLIL::Module *intfmodule = intf.second; RTLIL::Module *intfmodule = intf.second;
for (auto w : intfmodule->wires()){ for (auto w : intfmodule->wires()){
auto wire = std::make_unique<AstNode>(AST_WIRE, std::make_unique<AstNode>(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true))); auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
std::string newname = log_id(w->name); std::string newname = log_id(w->name);
newname = intfname + "." + newname; newname = intfname + "." + newname;
wire->str = newname; wire->str = newname;
@ -1615,9 +1617,9 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
if (design->module(interface_type) != nullptr) { if (design->module(interface_type) != nullptr) {
// Add a cell to the module corresponding to the interface port such that // Add a cell to the module corresponding to the interface port such that
// it can further propagated down if needed: // it can further propagated down if needed:
auto celltype_for_intf = std::make_unique<AstNode>(AST_CELLTYPE); auto celltype_for_intf = std::make_unique<AstNode>(loc, AST_CELLTYPE);
celltype_for_intf->str = interface_type; celltype_for_intf->str = interface_type;
auto cell_for_intf = std::make_unique<AstNode>(AST_CELL, std::move(celltype_for_intf)); auto cell_for_intf = std::make_unique<AstNode>(loc, AST_CELL, std::move(celltype_for_intf));
cell_for_intf->str = name_port + "_inst_from_top_dummy"; cell_for_intf->str = name_port + "_inst_from_top_dummy";
new_ast->children.push_back(std::move(cell_for_intf)); new_ast->children.push_back(std::move(cell_for_intf));
@ -1824,8 +1826,9 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
rewritten.reserve(GetSize(parameters)); rewritten.reserve(GetSize(parameters));
auto new_ast = ast->clone(); auto new_ast = ast->clone();
auto loc = ast->location;
if (!new_ast->attributes.count(ID::hdlname)) if (!new_ast->attributes.count(ID::hdlname))
new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name.substr(1))); new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(loc, stripped_name.substr(1)));
para_counter = 0; para_counter = 0;
for (auto& child : new_ast->children) { for (auto& child : new_ast->children) {
@ -1849,12 +1852,12 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
if (param_has_no_default(child)) if (param_has_no_default(child))
child->children.insert(child->children.begin(), nullptr); child->children.insert(child->children.begin(), nullptr);
if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) { if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) {
child->children[0] = std::make_unique<AstNode>(AST_REALVALUE); child->children[0] = std::make_unique<AstNode>(loc, AST_REALVALUE);
child->children[0]->realvalue = std::stod(it->second.decode_string()); child->children[0]->realvalue = std::stod(it->second.decode_string());
} else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0) } else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0)
child->children[0] = AstNode::mkconst_str(it->second.decode_string()); child->children[0] = AstNode::mkconst_str(loc, it->second.decode_string());
else else
child->children[0] = AstNode::mkconst_bits(it->second.to_bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); child->children[0] = AstNode::mkconst_bits(loc, it->second.to_bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
rewritten.insert(it->first); rewritten.insert(it->first);
} }
@ -1862,12 +1865,12 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
for (const auto &param : parameters) { for (const auto &param : parameters) {
if (rewritten.count(param.first)) if (rewritten.count(param.first))
continue; continue;
auto defparam = std::make_unique<AstNode>(AST_DEFPARAM, std::make_unique<AstNode>(AST_IDENTIFIER)); auto defparam = std::make_unique<AstNode>(loc, AST_DEFPARAM, std::make_unique<AstNode>(loc, AST_IDENTIFIER));
defparam->children[0]->str = param.first.str(); defparam->children[0]->str = param.first.str();
if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0) if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string())); defparam->children.push_back(AstNode::mkconst_str(loc, param.second.decode_string()));
else else
defparam->children.push_back(AstNode::mkconst_bits(param.second.to_bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); defparam->children.push_back(AstNode::mkconst_bits(loc, param.second.to_bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
new_ast->children.push_back(std::move(defparam)); new_ast->children.push_back(std::move(defparam));
} }
@ -1922,7 +1925,7 @@ void AstNode::input_error(const char *format, ...) const
{ {
va_list ap; va_list ap;
va_start(ap, format); va_start(ap, format);
logv_file_error(location.filename, location.first_line, format, ap); logv_file_error(*location.begin.filename, location.begin.line, format, ap);
} }
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

11
frontends/ast/ast.h
View file

@ -28,6 +28,7 @@
#include "kernel/rtlil.h" #include "kernel/rtlil.h"
#include "kernel/fmt.h" #include "kernel/fmt.h"
#include "frontends/verilog/verilog_location.h"
#include <stdint.h> #include <stdint.h>
#include <set> #include <set>
@ -162,13 +163,7 @@ namespace AST
AST_BIND AST_BIND
}; };
struct AstSrcLocType { using AstSrcLocType = location;
std::string filename;
unsigned int first_line, last_line;
unsigned int first_column, last_column;
AstSrcLocType() : filename(""), first_line(0), last_line(0), first_column(0), last_column(0) {}
AstSrcLocType(std::string _filename, int _first_line, int _first_column, int _last_line, int _last_column) : filename(_filename), first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}
};
// convert an node type to a string (e.g. for debug output) // convert an node type to a string (e.g. for debug output)
std::string type2str(AstNodeType type); std::string type2str(AstNodeType type);
@ -407,7 +402,7 @@ namespace AST
// this must be set by the language frontend before parsing the sources // this must be set by the language frontend before parsing the sources
// the AstNode constructor then uses current_filename and get_line_num() // the AstNode constructor then uses current_filename and get_line_num()
// to initialize the filename and linenum properties of new nodes // to initialize the filename and linenum properties of new nodes
extern std::string current_filename; // extern std::string current_filename;
// also set by the language frontend to control some AST processing // also set by the language frontend to control some AST processing
extern bool sv_mode_but_global_and_used_for_literally_one_condition; extern bool sv_mode_but_global_and_used_for_literally_one_condition;

67
frontends/ast/genrtlil.cc
View file

@ -45,7 +45,7 @@ using namespace AST_INTERNAL;
// helper function for creating RTLIL code for unary operations // helper function for creating RTLIL code for unary operations
static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true) static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
{ {
IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++); IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, type); RTLIL::Cell *cell = current_module->addCell(name, type);
set_src_attr(cell, that); set_src_attr(cell, that);
@ -77,7 +77,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
return; return;
} }
IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++); IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, ID($pos)); RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
set_src_attr(cell, that); set_src_attr(cell, that);
@ -104,7 +104,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
// helper function for creating RTLIL code for binary operations // helper function for creating RTLIL code for binary operations
static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{ {
IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++); IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, type); RTLIL::Cell *cell = current_module->addCell(name, type);
set_src_attr(cell, that); set_src_attr(cell, that);
@ -138,7 +138,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
log_assert(cond.size() == 1); log_assert(cond.size() == 1);
std::stringstream sstr; std::stringstream sstr;
sstr << "$ternary$" << RTLIL::encode_filename(that->location.filename) << ":" << that->location.first_line << "$" << (autoidx++); sstr << "$ternary$" << RTLIL::encode_filename(*that->location.begin.filename) << ":" << that->location.begin.line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux)); RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
set_src_attr(cell, that); set_src_attr(cell, that);
@ -195,12 +195,12 @@ struct AST_INTERNAL::LookaheadRewriter
if (node->lookahead) { if (node->lookahead) {
log_assert(node->type == AST_IDENTIFIER); log_assert(node->type == AST_IDENTIFIER);
if (!lookaheadids.count(node->str)) { if (!lookaheadids.count(node->str)) {
auto wire = std::make_unique<AstNode>(AST_WIRE); auto wire = std::make_unique<AstNode>(node->location, AST_WIRE);
for (auto& c : node->id2ast->children) for (auto& c : node->id2ast->children)
wire->children.push_back(c->clone()); wire->children.push_back(c->clone());
wire->fixup_hierarchy_flags(); wire->fixup_hierarchy_flags();
wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++); wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++);
wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire->set_attribute(ID::nosync, AstNode::mkconst_int(node->location, 1, false));
wire->is_logic = true; wire->is_logic = true;
while (wire->simplify(true, 1, -1, false)) { } while (wire->simplify(true, 1, -1, false)) { }
lookaheadids[node->str] = make_pair(node->id2ast, wire.get()); lookaheadids[node->str] = make_pair(node->id2ast, wire.get());
@ -271,6 +271,7 @@ struct AST_INTERNAL::LookaheadRewriter
// top->dumpVlog(nullptr, "REWRITE-BEFORE> "); // top->dumpVlog(nullptr, "REWRITE-BEFORE> ");
AstNode *block = nullptr; AstNode *block = nullptr;
auto loc = top->location;
for (auto& c : top->children) for (auto& c : top->children)
if (c->type == AST_BLOCK) { if (c->type == AST_BLOCK) {
@ -284,18 +285,18 @@ struct AST_INTERNAL::LookaheadRewriter
for (auto it : lookaheadids) for (auto it : lookaheadids)
{ {
auto ref_orig = std::make_unique<AstNode>(AST_IDENTIFIER); auto ref_orig = std::make_unique<AstNode>(loc, AST_IDENTIFIER);
ref_orig->str = it.second.first->str; ref_orig->str = it.second.first->str;
ref_orig->id2ast = it.second.first; ref_orig->id2ast = it.second.first;
ref_orig->was_checked = true; ref_orig->was_checked = true;
auto ref_temp = std::make_unique<AstNode>(AST_IDENTIFIER); auto ref_temp = std::make_unique<AstNode>(loc, AST_IDENTIFIER);
ref_temp->str = it.second.second->str; ref_temp->str = it.second.second->str;
ref_temp->id2ast = it.second.second; ref_temp->id2ast = it.second.second;
ref_temp->was_checked = true; ref_temp->was_checked = true;
auto init_assign = std::make_unique<AstNode>(AST_ASSIGN_EQ, ref_temp->clone(), ref_orig->clone()); auto init_assign = std::make_unique<AstNode>(loc, AST_ASSIGN_EQ, ref_temp->clone(), ref_orig->clone());
auto final_assign = std::make_unique<AstNode>(AST_ASSIGN_LE, std::move(ref_orig), std::move(ref_temp)); auto final_assign = std::make_unique<AstNode>(loc, AST_ASSIGN_LE, std::move(ref_orig), std::move(ref_temp));
block->children.insert(block->children.begin(), std::move(init_assign)); block->children.insert(block->children.begin(), std::move(init_assign));
block->children.push_back(std::move(final_assign)); block->children.push_back(std::move(final_assign));
@ -347,7 +348,7 @@ struct AST_INTERNAL::ProcessGenerator
LookaheadRewriter la_rewriter(always.get()); LookaheadRewriter la_rewriter(always.get());
// generate process and simple root case // generate process and simple root case
proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(always->location.filename).c_str(), always->location.first_line, autoidx++)); proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename).c_str(), always->location.begin.line, autoidx++));
set_src_attr(proc, always.get()); set_src_attr(proc, always.get());
for (auto &attr : always->attributes) { for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
@ -723,7 +724,7 @@ struct AST_INTERNAL::ProcessGenerator
if (ast->str == "$display" || ast->str == "$displayb" || ast->str == "$displayh" || ast->str == "$displayo" || if (ast->str == "$display" || ast->str == "$displayb" || ast->str == "$displayh" || ast->str == "$displayo" ||
ast->str == "$write" || ast->str == "$writeb" || ast->str == "$writeh" || ast->str == "$writeo") { ast->str == "$write" || ast->str == "$writeb" || ast->str == "$writeh" || ast->str == "$writeo") {
std::stringstream sstr; std::stringstream sstr;
sstr << ast->str << "$" << ast->location.filename << ":" << ast->location.first_line << "$" << (autoidx++); sstr << ast->str << "$" << ast->location.begin.filename << ":" << ast->location.begin.line << "$" << (autoidx++);
Wire *en = current_module->addWire(sstr.str() + "_EN", 1); Wire *en = current_module->addWire(sstr.str() + "_EN", 1);
set_src_attr(en, ast); set_src_attr(en, ast);
@ -766,8 +767,8 @@ struct AST_INTERNAL::ProcessGenerator
node->detectSignWidth(width, is_signed, nullptr); node->detectSignWidth(width, is_signed, nullptr);
VerilogFmtArg arg = {}; VerilogFmtArg arg = {};
arg.filename = node->location.filename; arg.filename = *node->location.begin.filename;
arg.first_line = node->location.first_line; arg.first_line = node->location.begin.line;
if (node->type == AST_CONSTANT && node->is_string) { if (node->type == AST_CONSTANT && node->is_string) {
arg.type = VerilogFmtArg::STRING; arg.type = VerilogFmtArg::STRING;
arg.str = node->bitsAsConst().decode_string(); arg.str = node->bitsAsConst().decode_string();
@ -793,7 +794,7 @@ struct AST_INTERNAL::ProcessGenerator
fmt.append_literal("\n"); fmt.append_literal("\n");
fmt.emit_rtlil(cell); fmt.emit_rtlil(cell);
} else if (!ast->str.empty()) { } else if (!ast->str.empty()) {
log_file_error(ast->location.filename, ast->location.first_line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str()); log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str());
} }
break; break;
@ -813,7 +814,7 @@ struct AST_INTERNAL::ProcessGenerator
IdString cellname; IdString cellname;
if (ast->str.empty()) if (ast->str.empty())
cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(ast->location.filename).c_str(), ast->location.first_line, autoidx++); cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(*ast->location.begin.filename).c_str(), ast->location.begin.line, autoidx++);
else else
cellname = ast->str; cellname = ast->str;
check_unique_id(current_module, cellname, ast, "procedural assertion"); check_unique_id(current_module, cellname, ast, "procedural assertion");
@ -843,7 +844,7 @@ struct AST_INTERNAL::ProcessGenerator
set_src_attr(cell, ast); set_src_attr(cell, ast);
for (auto &attr : ast->attributes) { for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_file_error(ast->location.filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
cell->setParam(ID::FLAVOR, flavor); cell->setParam(ID::FLAVOR, flavor);
@ -1503,7 +1504,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
RTLIL::SigSpec sig = realAsConst(width_hint); RTLIL::SigSpec sig = realAsConst(width_hint);
log_file_warning(location.filename, location.first_line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig)); log_file_warning(*location.begin.filename, location.begin.line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
return sig; return sig;
} }
@ -1535,7 +1536,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (dynamic_cast<RTLIL::Binding*>(current_module)) { if (dynamic_cast<RTLIL::Binding*>(current_module)) {
/* nothing to do here */ /* nothing to do here */
} else if (flag_autowire) } else if (flag_autowire)
log_file_warning(location.filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str()); log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str.c_str());
else else
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
} }
@ -1610,7 +1611,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
auto fake_ast = std::make_unique<AstNode>(AST_NONE, clone(), children[0]->children.size() >= 2 ? auto fake_ast = std::make_unique<AstNode>(children[0]->location, AST_NONE, clone(), children[0]->children.size() >= 2 ?
children[0]->children[1]->clone() : children[0]->children[0]->clone()); children[0]->children[1]->clone() : children[0]->children[0]->clone());
fake_ast->children[0]->delete_children(); fake_ast->children[0]->delete_children();
if (member_node) if (member_node)
@ -1640,10 +1641,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset = source_width - (chunk.offset + chunk.width); chunk.offset = source_width - (chunk.offset + chunk.width);
if (chunk.offset > chunk_left || chunk.offset + chunk.width < chunk_right) { if (chunk.offset > chunk_left || chunk.offset + chunk.width < chunk_right) {
if (chunk.width == 1) if (chunk.width == 1)
log_file_warning(location.filename, location.first_line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n", log_file_warning(*location.begin.filename, location.begin.line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
str.c_str()); str.c_str());
else else
log_file_warning(location.filename, location.first_line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n", log_file_warning(*location.begin.filename, location.begin.line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width); children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
} else { } else {
@ -1657,10 +1658,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset += add_undef_bits_lsb; chunk.offset += add_undef_bits_lsb;
} }
if (add_undef_bits_lsb) if (add_undef_bits_lsb)
log_file_warning(location.filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n", log_file_warning(*location.begin.filename, location.begin.line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb); children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
if (add_undef_bits_msb) if (add_undef_bits_msb)
log_file_warning(location.filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n", log_file_warning(*location.begin.filename, location.begin.line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb); children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
} }
} }
@ -1934,7 +1935,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MEMRD: case AST_MEMRD:
{ {
std::stringstream sstr; std::stringstream sstr;
sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(location.filename) << ":" << location.first_line << "$" << (autoidx++); sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd)); RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
set_src_attr(cell, this); set_src_attr(cell, this);
@ -1972,7 +1973,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MEMINIT: case AST_MEMINIT:
{ {
std::stringstream sstr; std::stringstream sstr;
sstr << "$meminit$" << str << "$" << RTLIL::encode_filename(location.filename) << ":" << location.first_line << "$" << (autoidx++); sstr << "$meminit$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
SigSpec en_sig = children[2]->genRTLIL(); SigSpec en_sig = children[2]->genRTLIL();
@ -2017,7 +2018,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
IdString cellname; IdString cellname;
if (str.empty()) if (str.empty())
cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(location.filename).c_str(), location.first_line, autoidx++); cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++);
else else
cellname = str; cellname = str;
check_unique_id(current_module, cellname, this, "procedural assertion"); check_unique_id(current_module, cellname, this, "procedural assertion");
@ -2060,7 +2061,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
new_left.append(left[i]); new_left.append(left[i]);
new_right.append(right[i]); new_right.append(right[i]);
} }
log_file_warning(location.filename, location.first_line, "Ignoring assignment to constant bits:\n" log_file_warning(*location.begin.filename, location.begin.line, "Ignoring assignment to constant bits:\n"
" old assignment: %s = %s\n new assignment: %s = %s.\n", " old assignment: %s = %s\n new assignment: %s = %s.\n",
log_signal(left), log_signal(right), log_signal(left), log_signal(right),
log_signal(new_left), log_signal(new_right)); log_signal(new_left), log_signal(new_right));
@ -2095,7 +2096,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str; IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
const AstNode *value = child->children[0].get(); const AstNode *value = child->children[0].get();
if (value->type == AST_REALVALUE) if (value->type == AST_REALVALUE)
log_file_warning(location.filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n", log_file_warning(*location.begin.filename, location.begin.line, "Replacing floating point parameter %s.%s = %f with string.\n",
log_id(cell), log_id(paraname), value->realvalue); log_id(cell), log_id(paraname), value->realvalue);
else if (value->type != AST_CONSTANT) else if (value->type != AST_CONSTANT)
input_error("Parameter %s.%s with non-constant value!\n", input_error("Parameter %s.%s with non-constant value!\n",
@ -2192,14 +2193,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int sz = children.size(); int sz = children.size();
if (str == "$info") { if (str == "$info") {
if (sz > 0) if (sz > 0)
log_file_info(location.filename, location.first_line, "%s.\n", children[0]->str.c_str()); log_file_info(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str());
else else
log_file_info(location.filename, location.first_line, "\n"); log_file_info(*location.begin.filename, location.begin.line, "\n");
} else if (str == "$warning") { } else if (str == "$warning") {
if (sz > 0) if (sz > 0)
log_file_warning(location.filename, location.first_line, "%s.\n", children[0]->str.c_str()); log_file_warning(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str());
else else
log_file_warning(location.filename, location.first_line, "\n"); log_file_warning(*location.begin.filename, location.begin.line, "\n");
} else if (str == "$error") { } else if (str == "$error") {
if (sz > 0) if (sz > 0)
input_error("%s.\n", children[0]->str.c_str()); input_error("%s.\n", children[0]->str.c_str());

562
frontends/ast/simplify.cc
View file

File diff suppressed because it is too large Load diff

2
frontends/verilog/.gitignore vendored
View file

@ -2,6 +2,4 @@ verilog_lexer.cc
verilog_parser.output verilog_parser.output
verilog_parser.tab.cc verilog_parser.tab.cc
verilog_parser.tab.hh verilog_parser.tab.hh
position.hh
location.hh
stack.hh stack.hh

4
frontends/verilog/Makefile.inc
View file

@ -3,11 +3,9 @@ GENFILES += frontends/verilog/verilog_parser.tab.cc
GENFILES += frontends/verilog/verilog_parser.tab.hh GENFILES += frontends/verilog/verilog_parser.tab.hh
GENFILES += frontends/verilog/verilog_parser.output GENFILES += frontends/verilog/verilog_parser.output
GENFILES += frontends/verilog/verilog_lexer.cc GENFILES += frontends/verilog/verilog_lexer.cc
GENFILES += frontends/verilog/location.hh
GENFILES += frontends/verilog/position.hh
GENFILES += frontends/verilog/stack.hh GENFILES += frontends/verilog/stack.hh
frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y frontends/verilog/verilog_location.h
$(Q) mkdir -p $(dir $@) $(Q) mkdir -p $(dir $@)
$(P) $(BISON) -Wall -Werror -o $@ -d -r all -b frontends/verilog/verilog_parser $< $(P) $(BISON) -Wall -Werror -o $@ -d -r all -b frontends/verilog/verilog_parser $<

2
frontends/verilog/const2ast.cc
View file

@ -47,7 +47,7 @@ using namespace VERILOG_FRONTEND;
std::string ConstParser::fmt_maybe_loc(std::string msg) { std::string ConstParser::fmt_maybe_loc(std::string msg) {
std::string s; std::string s;
s += stringf("%s:%d:", loc.filename, loc.first_line); s += stringf("%s:%d:", loc.begin.filename->c_str(), loc.begin.line);
s += msg; s += msg;
return s; return s;

25
frontends/verilog/verilog_frontend.cc
View file

@ -33,6 +33,7 @@
#include "verilog_frontend.h" #include "verilog_frontend.h"
#include "verilog_lexer.h" #include "verilog_lexer.h"
#include "verilog_error.h" #include "verilog_error.h"
#include "verilog_location.h"
#include "preproc.h" #include "preproc.h"
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include "libs/sha1/sha1.h" #include "libs/sha1/sha1.h"
@ -277,8 +278,8 @@ struct VerilogFrontend : public Frontend {
std::list<std::string> include_dirs; std::list<std::string> include_dirs;
std::list<std::string> attributes; std::list<std::string> attributes;
ParseMode parse_mode; ParseMode parse_mode = {};
ParseState parse_state; ParseState parse_state = {};
parse_mode.sv = false; parse_mode.sv = false;
parse_mode.formal = false; parse_mode.formal = false;
parse_mode.noassert = false; parse_mode.noassert = false;
@ -479,11 +480,6 @@ struct VerilogFrontend : public Frontend {
break; break;
} }
VerilogLexer lexer(&parse_state, &parse_mode, &filename);
frontend_verilog_yy::parser parser(&lexer, &parse_state, &parse_mode);
lexer.set_debug(flag_debug_lexer);
parser.set_debug_level(flag_debug_parser ? 1 : 0);
if (parse_mode.formal || !flag_nosynthesis) if (parse_mode.formal || !flag_nosynthesis)
defines_map.add(parse_mode.formal ? "FORMAL" : "SYNTHESIS", "1"); defines_map.add(parse_mode.formal ? "FORMAL" : "SYNTHESIS", "1");
@ -495,13 +491,9 @@ struct VerilogFrontend : public Frontend {
parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str()); parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str());
AST::sv_mode_but_global_and_used_for_literally_one_condition = parse_mode.sv; AST::sv_mode_but_global_and_used_for_literally_one_condition = parse_mode.sv;
AstSrcLocType top_loc = AstSrcLocType ( "read_verilog", 0, 0, 0, 0);
parse_state.current_ast = new AST::AstNode(top_loc, AST::AST_DESIGN);
parse_state.lexin = f;
std::string code_after_preproc; std::string code_after_preproc;
parse_state.lexin = f;
if (!flag_nopp) { if (!flag_nopp) {
code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode); code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode);
if (flag_ppdump) if (flag_ppdump)
@ -509,6 +501,15 @@ struct VerilogFrontend : public Frontend {
parse_state.lexin = new std::istringstream(code_after_preproc); parse_state.lexin = new std::istringstream(code_after_preproc);
} }
auto filename_shared = std::make_shared<std::string>(filename);
auto top_loc = location();
top_loc.begin.filename = filename_shared;
parse_state.current_ast = new AST::AstNode(top_loc, AST::AST_DESIGN);
VerilogLexer lexer(&parse_state, &parse_mode, filename_shared);
frontend_verilog_yy::parser parser(&lexer, &parse_state, &parse_mode);
lexer.set_debug(flag_debug_lexer);
parser.set_debug_level(flag_debug_parser ? 1 : 0);
// make package typedefs available to parser // make package typedefs available to parser
add_package_types(parse_state.pkg_user_types, design->verilog_packages); add_package_types(parse_state.pkg_user_types, design->verilog_packages);

6
frontends/verilog/verilog_lexer.h
View file

@ -5,6 +5,7 @@
#include "frontends/ast/ast.h" #include "frontends/ast/ast.h"
#include "frontends/verilog/verilog_parser.tab.hh" #include "frontends/verilog/verilog_parser.tab.hh"
#include <string> #include <string>
#include <memory>
YOSYS_NAMESPACE_BEGIN YOSYS_NAMESPACE_BEGIN
@ -15,7 +16,7 @@ namespace VERILOG_FRONTEND {
ParseMode* mode; ParseMode* mode;
public: public:
parser::location_type out_loc; // TODO private? parser::location_type out_loc; // TODO private?
VerilogLexer(ParseState* e, ParseMode* m, std::string* filename) : frontend_verilog_yyFlexLexer(e->lexin), extra(e), mode(m) { VerilogLexer(ParseState* e, ParseMode* m, std::shared_ptr<string> filename) : frontend_verilog_yyFlexLexer(e->lexin), extra(e), mode(m) {
out_loc.begin.filename = filename; out_loc.begin.filename = filename;
} }
~VerilogLexer() override {} ~VerilogLexer() override {}
@ -27,7 +28,8 @@ namespace VERILOG_FRONTEND {
return parser::make_FRONTEND_VERILOG_YYEOF(out_loc); return parser::make_FRONTEND_VERILOG_YYEOF(out_loc);
} }
private: private:
std::vector<std::string> fn_stack; std::shared_ptr<std::string> current_filename;
std::vector<std::shared_ptr<std::string>> fn_stack;
std::vector<int> ln_stack; std::vector<int> ln_stack;
int LexerInput(char* buf, int max_size) override { int LexerInput(char* buf, int max_size) override {
return readsome(*extra->lexin, buf, max_size); return readsome(*extra->lexin, buf, max_size);

38
frontends/verilog/verilog_lexer.l
View file

@ -50,8 +50,10 @@
#include "frontends/verilog/verilog_lexer.h" #include "frontends/verilog/verilog_lexer.h"
#include "frontends/ast/ast.h" #include "frontends/ast/ast.h"
#include "frontends/verilog/verilog_location.h"
#include "kernel/log.h" #include "kernel/log.h"
#include <vector> #include <vector>
#include <memory>
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
using namespace AST; using namespace AST;
@ -73,7 +75,7 @@ YOSYS_NAMESPACE_END
if (mode->sv) return _tok; \ if (mode->sv) return _tok; \
log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\ log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
"recognized unless read_verilog is called with -sv!\n", YYText(), \ "recognized unless read_verilog is called with -sv!\n", YYText(), \
AST::current_filename.c_str(), yylineno); \ current_filename->c_str(), yylineno); \
string_t val = std::make_unique<std::string>(std::string("\\") + YYText()); \ string_t val = std::make_unique<std::string>(std::string("\\") + YYText()); \
return parser::make_TOK_ID(std::move(val), out_loc); return parser::make_TOK_ID(std::move(val), out_loc);
@ -85,16 +87,17 @@ YOSYS_NAMESPACE_END
// result = readsome(*extra->lexin, buf, max_size) // result = readsome(*extra->lexin, buf, max_size)
#define YY_USER_ACTION \ #define YY_USER_ACTION \
out_loc.begin = out_loc.end; \ out_loc.step(); \
for(int i = 0; YYText()[i] != '\0'; ++i){ \ for(int i = 0; YYText()[i] != '\0'; ++i){ \
if(YYText()[i] == '\n') { \ if(YYText()[i] == '\n') { \
out_loc.end.line++; \ out_loc.lines(); \
out_loc.end.column = 1; \ } \
} \ else { \
else { \ out_loc.columns(); \
out_loc.end.column++; \ } \
} \ } \
} out_loc.begin.filename = current_filename; \
out_loc.end.filename = current_filename;
#define YY_BREAK \ #define YY_BREAK \
break; break;
@ -175,11 +178,12 @@ TIME_SCALE_SUFFIX [munpf]?s
<INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* { <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
fn_stack.push_back(current_filename); fn_stack.push_back(current_filename);
ln_stack.push_back(yylineno); ln_stack.push_back(yylineno);
current_filename = YYText()+11; std::string filename = YYText()+11;
if (!current_filename.empty() && current_filename.front() == '"') if (!filename.empty() && filename.front() == '"')
current_filename = current_filename.substr(1); filename = filename.substr(1);
if (!current_filename.empty() && current_filename.back() == '"') if (!filename.empty() && filename.back() == '"')
current_filename = current_filename.substr(0, current_filename.size()-1); filename = filename.substr(0, filename.size()-1);
current_filename = std::make_shared<std::string>(filename);
yylineno = (0); yylineno = (0);
out_loc.begin.line = out_loc.end.line = 0; out_loc.begin.line = out_loc.end.line = 0;
} }
@ -201,7 +205,7 @@ TIME_SCALE_SUFFIX [munpf]?s
while (*p == ' ' || *p == '\t') p++; while (*p == ' ' || *p == '\t') p++;
const char *q = *p ? p + 1 : p; const char *q = *p ? p + 1 : p;
while (*q && *q != '"') q++; while (*q && *q != '"') q++;
current_filename = std::string(p).substr(1, q-p-1); current_filename = std::make_shared<std::string>(std::string(p).substr(1, q-p-1));
} }
"`file_notfound "[^\n]* { "`file_notfound "[^\n]* {

650
frontends/verilog/verilog_parser.y
View file

File diff suppressed because it is too large Load diff

4
kernel/rtlil.cc
View file

@ -5695,7 +5695,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
{ {
cover("kernel.rtlil.sigspec.parse"); cover("kernel.rtlil.sigspec.parse");
AST::current_filename = "input"; // AST::current_filename = "input";
std::vector<std::string> tokens; std::vector<std::string> tokens;
sigspec_parse_split(tokens, str, ','); sigspec_parse_split(tokens, str, ',');
@ -5711,7 +5711,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') { if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
cover("kernel.rtlil.sigspec.parse.const"); cover("kernel.rtlil.sigspec.parse.const");
VERILOG_FRONTEND::ConstParser p; VERILOG_FRONTEND::ConstParser p{location()};
auto ast = p.const2ast(netname); auto ast = p.const2ast(netname);
if (ast == nullptr) if (ast == nullptr)
return false; return false;