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macc: Stop using the B port

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The B port is for single-bit summands. These can just as well be
represented as an additional summand on the A port (which supports
summands of arbitrary width). An upcoming `$macc_v2` cell won't be
special-casing single-bit summands in any way.

In preparation, make the following changes:

 * remove the `bit_ports` field from the `Macc` helper (instead add any
   single-bit summands to `ports` next to other summands)

 * leave `B` empty on cells emitted from `Macc::to_cell`
This commit is contained in:
Martin Povišer 2024-12-13 18:10:10 +01:00 • committed by Emil J. Tywoniak
parent 8fd40942e9
commit 652a1b9806
10 changed files with 89 additions and 51 deletions
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13
passes/tests/test_cell.cc
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@ -201,18 +201,19 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
this_port.do_subtract = xorshift32(2) == 1;
macc.ports.push_back(this_port);
}
wire = module->addWire(ID::B);
wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1);
wire->port_input = true;
macc.bit_ports = wire;
// Macc::to_cell sets the input ports
macc.to_cell(cell);
wire = module->addWire(ID::Y);
wire->width = width;
wire->port_output = true;
cell->setPort(ID::Y, wire);
macc.to_cell(cell);
// override the B input (macc helpers always sets an empty vector)
wire = module->addWire(ID::B);
wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1);
wire->port_input = true;
cell->setPort(ID::B, wire);
}
if (cell_type == ID($lut))