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Eddie Hung 2019-08-20 20:07:38 -07:00
parent affe9c9c1a
commit 64d62710de
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techlibs/xilinx/cells_sim.v
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@ -299,7 +299,7 @@ endmodule
module RAM32X1D ( module RAM32X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc_arrival=11530 *) output DPO, SPO, (* abc_arrival=1153 *) output DPO, SPO,
input D, input D,
input WCLK, input WCLK,
input WE, input WE,