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Merge 13ab5d4a67 into 8869ce61dc

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Alain Dargelas 2026-06-15 10:18:01 +02:00 • committed by GitHub
commit 64c8250b39
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2 changed files with 43 additions and 5 deletions
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15
backends/verilog/verilog_backend.cc
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@ -456,21 +456,26 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
if (wire->attributes.count(ID::single_bit_vector))
range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
}
// Emit `signed` for wires/ports whose RTLIL is_signed flag is set.
// Without this, an `output signed [N:0] o` was silently demoted to plain
// `output [N:0] o` on write, losing the declared signedness in a
// read_verilog -> write_verilog round-trip.
const char *signed_kw = wire->is_signed ? " signed" : "";
if (wire->port_input && !wire->port_output)
f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "input%s%s %s;\n", indent, signed_kw, range, id(wire->name));
if (!wire->port_input && wire->port_output)
f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "output%s%s %s;\n", indent, signed_kw, range, id(wire->name));
if (wire->port_input && wire->port_output)
f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "inout%s%s %s;\n", indent, signed_kw, range, id(wire->name));
if (reg_wires.count(wire->name)) {
f << stringf("%s" "reg%s %s", indent, range, id(wire->name));
f << stringf("%s" "reg%s%s %s", indent, signed_kw, range, id(wire->name));
if (wire->attributes.count(ID::init)) {
f << stringf(" = ");
dump_const(f, wire->attributes.at(ID::init));
}
f << stringf(";\n");
} else
f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "wire%s%s %s;\n", indent, signed_kw, range, id(wire->name));
#endif
}