Docs: interactive investigation

More `literalinclude` and references to source.
Adding `example_show.ys` and `example_lscd.ys`.
Rename `example_00` et al to `example_first` et al.
Also some other minor tidying.

docs/source/code_examples/show/example.out

@@ -0,0 +1,54 @@
+
+-- Executing script file `example_lscd.ys' --
+
+1. Executing Verilog-2005 frontend: example.v
+Parsing Verilog input from `example.v' to AST representation.
+Generating RTLIL representation for module `\example'.
+Successfully finished Verilog frontend.
+echo on
+
+yosys> ls
+
+1 modules:
+  example
+
+yosys> cd example
+
+yosys [example]> ls
+
+8 wires:
+  $0\y[1:0]
+  $add$example.v:5$2_Y
+  $ternary$example.v:5$3_Y
+  a
+  b
+  c
+  clk
+  y
+
+2 cells:
+  $add$example.v:5$2
+  $ternary$example.v:5$3
+
+1 processes:
+  $proc$example.v:3$1
+
+yosys [example]> dump $2
+
+
+  attribute \src "example.v:5.22-5.27"
+  cell $add $add$example.v:5$2
+    parameter \Y_WIDTH 2
+    parameter \B_WIDTH 1
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \A_SIGNED 0
+    connect \Y $add$example.v:5$2_Y
+    connect \B \b
+    connect \A \a
+  end
+
+yosys [example]> cd ..
+
+yosys> echo off
+echo off