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add example memory test

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This commit is contained in:
N. Engelhardt 2023-11-30 19:35:43 +01:00
parent f810bd88f5
commit 64609afe2c
7 changed files with 1213 additions and 1 deletions
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tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys Normal file
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read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
read_verilog -formal bram_tdp.v bram_tdp_tb.v
hierarchy -top TB
proc
sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd