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Fix up ExclusiveDatabase with @cliffordwolf's help
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@ -29,54 +29,53 @@ struct ExclusiveDatabase
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Module *module;
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Module *module;
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const SigMap &sigmap;
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const SigMap &sigmap;
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dict<SigBit, SigSpec> sig_cmp_prev;
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dict<SigBit, std::pair<SigSpec,Const>> sig_cmp_prev;
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dict<SigSpec, pool<SigSpec>> sig_exclusive;
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ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
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ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
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{
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{
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SigSpec a_port, b_port, y_port;
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SigSpec const_sig, nonconst_sig, y_port;
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for (auto cell : module->cells()) {
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for (auto cell : module->cells()) {
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if (cell->type == "$eq") {
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if (cell->type == "$eq") {
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a_port = sigmap(cell->getPort("\\A"));
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nonconst_sig = sigmap(cell->getPort("\\A"));
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b_port = sigmap(cell->getPort("\\B"));
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const_sig = sigmap(cell->getPort("\\B"));
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if (!b_port.is_fully_const()) {
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if (!const_sig.is_fully_const()) {
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if (!a_port.is_fully_const())
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if (!nonconst_sig.is_fully_const())
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continue;
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continue;
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std::swap(a_port, b_port);
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std::swap(nonconst_sig, const_sig);
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}
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}
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y_port = sigmap(cell->getPort("\\Y"));
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y_port = sigmap(cell->getPort("\\Y"));
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}
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}
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else if (cell->type == "$logic_not") {
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else if (cell->type == "$logic_not") {
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a_port = sigmap(cell->getPort("\\A"));
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nonconst_sig = sigmap(cell->getPort("\\A"));
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b_port = Const(RTLIL::S0, GetSize(a_port));
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const_sig = Const(RTLIL::S0, GetSize(nonconst_sig));
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y_port = sigmap(cell->getPort("\\Y"));
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y_port = sigmap(cell->getPort("\\Y"));
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}
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}
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else continue;
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else continue;
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auto r = sig_exclusive[a_port].insert(b_port.as_const());
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log_assert(!nonconst_sig.empty());
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if (!r.second)
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log_assert(!const_sig.empty());
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continue;
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sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,const_sig.as_const());
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sig_cmp_prev[y_port] = a_port;
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}
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}
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}
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}
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bool query(const SigSpec& sig1, const SigSpec& sig2) const
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bool query(const SigSpec &sig) const
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{
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{
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// FIXME: O(N^2)
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SigSpec nonconst_sig;
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for (auto bit1 : sig1.bits()) {
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pool<Const> const_values;
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auto it = sig_cmp_prev.find(bit1);
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if (it == sig_cmp_prev.end())
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return false;
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for (auto bit2 : sig2.bits()) {
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for (auto bit : sig.bits()) {
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auto jt = sig_cmp_prev.find(bit2);
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auto it = sig_cmp_prev.find(bit);
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if (jt == sig_cmp_prev.end())
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if (it == sig_cmp_prev.end())
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return false;
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return false;
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if (it->second != jt->second)
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if (nonconst_sig.empty())
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return false;
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nonconst_sig = it->second.first;
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}
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else if (nonconst_sig != it->second.first)
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}
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return false;
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if (!const_values.insert(it->second.second).second)
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return false;
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}
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return true;
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return true;
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}
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}
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@ -178,8 +177,8 @@ struct MuxpackWorker
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Cell *prev_cell = sig_chain_prev.at(a_sig);
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Cell *prev_cell = sig_chain_prev.at(a_sig);
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log_assert(prev_cell);
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log_assert(prev_cell);
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SigSpec s_sig = sigmap(cell->getPort("\\S"));
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SigSpec s_sig = sigmap(cell->getPort("\\S"));
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SigSpec next_s_sig = sigmap(prev_cell->getPort("\\S"));
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s_sig.append(sigmap(prev_cell->getPort("\\S")));
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if (!excl_db.query(s_sig, next_s_sig))
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if (!excl_db.query(s_sig))
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goto start_cell;
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goto start_cell;
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}
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}
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