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Fix up ExclusiveDatabase with @cliffordwolf's help

This commit is contained in:
Eddie Hung 2019-06-21 11:45:31 -07:00
parent 63eb5cace9
commit 641b86d25f

View file

@ -29,54 +29,53 @@ struct ExclusiveDatabase
Module *module; Module *module;
const SigMap &sigmap; const SigMap &sigmap;
dict<SigBit, SigSpec> sig_cmp_prev; dict<SigBit, std::pair<SigSpec,Const>> sig_cmp_prev;
dict<SigSpec, pool<SigSpec>> sig_exclusive;
ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap) ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
{ {
SigSpec a_port, b_port, y_port; SigSpec const_sig, nonconst_sig, y_port;
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type == "$eq") { if (cell->type == "$eq") {
a_port = sigmap(cell->getPort("\\A")); nonconst_sig = sigmap(cell->getPort("\\A"));
b_port = sigmap(cell->getPort("\\B")); const_sig = sigmap(cell->getPort("\\B"));
if (!b_port.is_fully_const()) { if (!const_sig.is_fully_const()) {
if (!a_port.is_fully_const()) if (!nonconst_sig.is_fully_const())
continue; continue;
std::swap(a_port, b_port); std::swap(nonconst_sig, const_sig);
} }
y_port = sigmap(cell->getPort("\\Y")); y_port = sigmap(cell->getPort("\\Y"));
} }
else if (cell->type == "$logic_not") { else if (cell->type == "$logic_not") {
a_port = sigmap(cell->getPort("\\A")); nonconst_sig = sigmap(cell->getPort("\\A"));
b_port = Const(RTLIL::S0, GetSize(a_port)); const_sig = Const(RTLIL::S0, GetSize(nonconst_sig));
y_port = sigmap(cell->getPort("\\Y")); y_port = sigmap(cell->getPort("\\Y"));
} }
else continue; else continue;
auto r = sig_exclusive[a_port].insert(b_port.as_const()); log_assert(!nonconst_sig.empty());
if (!r.second) log_assert(!const_sig.empty());
continue; sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,const_sig.as_const());
sig_cmp_prev[y_port] = a_port; }
} }
}
bool query(const SigSpec& sig1, const SigSpec& sig2) const bool query(const SigSpec &sig) const
{ {
// FIXME: O(N^2) SigSpec nonconst_sig;
for (auto bit1 : sig1.bits()) { pool<Const> const_values;
auto it = sig_cmp_prev.find(bit1);
if (it == sig_cmp_prev.end())
return false;
for (auto bit2 : sig2.bits()) { for (auto bit : sig.bits()) {
auto jt = sig_cmp_prev.find(bit2); auto it = sig_cmp_prev.find(bit);
if (jt == sig_cmp_prev.end()) if (it == sig_cmp_prev.end())
return false; return false;
if (it->second != jt->second) if (nonconst_sig.empty())
return false; nonconst_sig = it->second.first;
} else if (nonconst_sig != it->second.first)
} return false;
if (!const_values.insert(it->second.second).second)
return false;
}
return true; return true;
} }
@ -178,8 +177,8 @@ struct MuxpackWorker
Cell *prev_cell = sig_chain_prev.at(a_sig); Cell *prev_cell = sig_chain_prev.at(a_sig);
log_assert(prev_cell); log_assert(prev_cell);
SigSpec s_sig = sigmap(cell->getPort("\\S")); SigSpec s_sig = sigmap(cell->getPort("\\S"));
SigSpec next_s_sig = sigmap(prev_cell->getPort("\\S")); s_sig.append(sigmap(prev_cell->getPort("\\S")));
if (!excl_db.query(s_sig, next_s_sig)) if (!excl_db.query(s_sig))
goto start_cell; goto start_cell;
} }