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More slimming

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This commit is contained in:
Eddie Hung 2019-06-13 13:29:03 -07:00
parent d39a5a77a9
commit 63e2f83632
1 changed files with 35 additions and 35 deletions
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70
kernel/consteval.h
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@ -397,8 +397,8 @@ struct ConstEvalAig
SigMap values_map; SigMap values_map;
//SigPool stop_signals; //SigPool stop_signals;
SigSet<RTLIL::Cell*> sig2driver; SigSet<RTLIL::Cell*> sig2driver;
std::set<RTLIL::Cell*> busy; //std::set<RTLIL::Cell*> busy;
std::vector<SigMap> stack; //std::vector<SigMap> stack;
//RTLIL::State defaultval; //RTLIL::State defaultval;
ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/ ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/
@ -422,16 +422,16 @@ struct ConstEvalAig
//stop_signals.clear(); //stop_signals.clear();
} }
void push() //void push()
{ //{
stack.push_back(values_map); // stack.push_back(values_map);
} //}
void pop() //void pop()
{ //{
values_map.swap(stack.back()); // values_map.swap(stack.back());
stack.pop_back(); // stack.pop_back();
} //}
void set(RTLIL::SigSpec sig, RTLIL::Const value) void set(RTLIL::SigSpec sig, RTLIL::Const value)
{ {
@ -450,14 +450,14 @@ struct ConstEvalAig
// stop_signals.add(sig); // stop_signals.add(sig);
//} //}
bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef) bool eval(RTLIL::Cell *cell /*, RTLIL::SigSpec &undef*/)
{ {
RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y"))); RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y")));
if (sig_y.is_fully_const()) if (sig_y.is_fully_const())
return true; return true;
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort("\\A");
if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) if (sig_a.size() > 0 && !eval(sig_a /*, undef, cell*/))
return false; return false;
RTLIL::Const eval_ret; RTLIL::Const eval_ret;
@ -473,7 +473,7 @@ struct ConstEvalAig
{ {
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort("\\B");
if (sig_b.size() > 0 && !eval(sig_b, undef, cell)) if (sig_b.size() > 0 && !eval(sig_b /*, undef, cell*/))
return false; return false;
if (sig_b == RTLIL::S0) { if (sig_b == RTLIL::S0) {
eval_ret = RTLIL::S0; eval_ret = RTLIL::S0;
@ -496,7 +496,7 @@ eval_end:
return true; return true;
} }
bool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL) bool eval(RTLIL::SigSpec &sig /*, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL*/)
{ {
//assign_map.apply(sig); //assign_map.apply(sig);
values_map.apply(sig); values_map.apply(sig);
@ -509,42 +509,42 @@ eval_end:
// return false; // return false;
//} //}
if (busy_cell) { //if (busy_cell) {
if (busy.count(busy_cell) > 0) { // if (busy.count(busy_cell) > 0) {
undef = sig; // undef = sig;
return false; // return false;
} // }
busy.insert(busy_cell); // busy.insert(busy_cell);
} //}
std::set<RTLIL::Cell*> driver_cells; std::set<RTLIL::Cell*> driver_cells;
sig2driver.find(sig, driver_cells); sig2driver.find(sig, driver_cells);
for (auto cell : driver_cells) { for (auto cell : driver_cells) {
if (!eval(cell, undef)) { if (!eval(cell /*, undef*/)) {
if (busy_cell) //if (busy_cell)
busy.erase(busy_cell); // busy.erase(busy_cell);
return false; return false;
} }
} }
if (busy_cell) //if (busy_cell)
busy.erase(busy_cell); // busy.erase(busy_cell);
values_map.apply(sig); values_map.apply(sig);
if (sig.is_fully_const()) if (sig.is_fully_const())
return true; return true;
for (auto &c : sig.chunks()) //for (auto &c : sig.chunks())
if (c.wire != NULL) // if (c.wire != NULL)
undef.append(c); // undef.append(c);
return false; return false;
} }
bool eval(RTLIL::SigSpec &sig) //bool eval(RTLIL::SigSpec &sig)
{ //{
RTLIL::SigSpec undef; // RTLIL::SigSpec undef;
return eval(sig, undef); // return eval(sig, undef);
} //}
}; };
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END