mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Improvements in "supercover" pass

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-02-27 11:45:13 -08:00
parent a58dbcf2ba
commit 63be3f3bab
1 changed files with 18 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

20
passes/sat/supercover.cc
View file

@ -54,17 +54,33 @@ struct SupercoverPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
SigMap sigmap(module);
pool<SigBit> handled_bits;
int cnt_wire = 0, cnt_bits = 0; int cnt_wire = 0, cnt_bits = 0;
log("Adding cover cells to module %s.\n", log_id(module)); log("Adding cover cells to module %s.\n", log_id(module));
for (auto wire : module->selected_wires()) for (auto wire : module->selected_wires())
{ {
bool counted_wire = false;
std::string src = wire->get_src_attribute(); std::string src = wire->get_src_attribute();
cnt_wire++;
for (auto bit : SigSpec(wire)) for (auto bit : sigmap(SigSpec(wire)))
{ {
if (bit.wire == nullptr)
continue;
if (handled_bits.count(bit))
continue;
SigSpec inv = module->Not(NEW_ID, bit); SigSpec inv = module->Not(NEW_ID, bit);
module->addCover(NEW_ID, bit, State::S1, src); module->addCover(NEW_ID, bit, State::S1, src);
module->addCover(NEW_ID, inv, State::S1, src); module->addCover(NEW_ID, inv, State::S1, src);
handled_bits.insert(bit);
if (!counted_wire) {
counted_wire = false;
cnt_wire++;
}
cnt_bits++; cnt_bits++;
} }
} }