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https://github.com/YosysHQ/yosys
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kernel/ff: Refactor FfData to enable FFs with async load.
- *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
This commit is contained in:
Marcelina Kościelnicka
parent
ec2b5548fe
commit
63b9df8693
10 changed files with 565 additions and 325 deletions
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@ -382,6 +382,69 @@ struct OptDffWorker
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}
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}
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if (ff.has_aload) {
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if (ff.sig_aload == (ff.pol_aload ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_aload == State::Sx)) {
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// Always-inactive enable — remove.
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log("Removing never-active async load on %s (%s) from module %s.\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_aload = false;
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changed = true;
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} else if (ff.sig_aload == (ff.pol_aload ? State::S1 : State::S0)) {
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// Always-active enable. Make a comb circuit, nuke the FF/latch.
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log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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initvals.remove_init(ff.sig_q);
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module->remove(cell);
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if (ff.has_sr) {
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SigSpec tmp;
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if (ff.is_fine) {
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if (ff.pol_set)
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tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set);
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else
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tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set);
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if (ff.pol_clr)
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module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
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else
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module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
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} else {
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if (ff.pol_set)
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tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set);
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else
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tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set));
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if (ff.pol_clr)
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module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);
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else
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module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);
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}
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} else if (ff.has_arst) {
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if (ff.is_fine) {
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if (ff.pol_arst)
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module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q);
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else
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module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q);
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} else {
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if (ff.pol_arst)
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module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q);
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else
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module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q);
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}
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} else {
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module->connect(ff.sig_q, ff.sig_ad);
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}
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did_something = true;
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continue;
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} else if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {
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log("Changing const-value async load to async reset on %s (%s) from module %s.\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_arst = true;
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ff.has_aload = false;
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ff.sig_arst = ff.sig_aload;
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ff.pol_arst = ff.pol_aload;
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ff.val_arst = ff.sig_ad.as_const();
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changed = true;
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}
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}
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if (ff.has_arst) {
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if (ff.sig_arst == (ff.pol_arst ? State::S0 : State::S1)) {
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// Always-inactive reset — remove.
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@ -414,111 +477,63 @@ struct OptDffWorker
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_srst = false;
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if (!ff.ce_over_srst)
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ff.has_en = false;
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ff.sig_d = ff.val_d = ff.val_srst;
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ff.d_is_const = true;
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ff.has_ce = false;
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ff.sig_d = ff.val_srst;
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changed = true;
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}
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}
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if (ff.has_en) {
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if (ff.sig_en == (ff.pol_en ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_en == State::Sx)) {
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if (ff.has_ce) {
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if (ff.sig_ce == (ff.pol_ce ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_ce == State::Sx)) {
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// Always-inactive enable — remove.
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if (ff.has_clk && ff.has_srst && !ff.ce_over_srst) {
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if (ff.has_srst && !ff.ce_over_srst) {
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log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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// FF with sync reset — connect the sync reset to D instead.
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ff.pol_en = ff.pol_srst;
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ff.sig_en = ff.sig_srst;
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ff.pol_ce = ff.pol_srst;
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ff.sig_ce = ff.sig_srst;
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ff.has_srst = false;
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ff.sig_d = ff.val_d = ff.val_srst;
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ff.d_is_const = true;
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ff.sig_d = ff.val_srst;
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changed = true;
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} else {
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log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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// The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver).
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ff.has_d = ff.has_en = ff.has_clk = false;
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// The D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver).
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ff.has_ce = ff.has_clk = ff.has_srst = false;
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changed = true;
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}
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} else if (ff.sig_en == (ff.pol_en ? State::S1 : State::S0)) {
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// Always-active enable.
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if (ff.has_clk) {
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// For FF, just remove the useless enable.
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log("Removing always-active EN on %s (%s) from module %s.\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_en = false;
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changed = true;
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} else {
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// For latches, make a comb circuit, nuke the latch.
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log("Handling always-active EN on %s (%s) from module %s (changing to combinatorial circuit).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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initvals.remove_init(ff.sig_q);
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module->remove(cell);
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if (ff.has_sr) {
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SigSpec tmp;
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if (ff.is_fine) {
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if (ff.pol_set)
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tmp = module->MuxGate(NEW_ID, ff.sig_d, State::S1, ff.sig_set);
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else
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tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_d, ff.sig_set);
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if (ff.pol_clr)
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module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
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else
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module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
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} else {
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if (ff.pol_set)
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tmp = module->Or(NEW_ID, ff.sig_d, ff.sig_set);
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else
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tmp = module->Or(NEW_ID, ff.sig_d, module->Not(NEW_ID, ff.sig_set));
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if (ff.pol_clr)
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module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);
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else
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module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);
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}
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} else if (ff.has_arst) {
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if (ff.is_fine) {
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if (ff.pol_arst)
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module->addMuxGate(NEW_ID, ff.sig_d, ff.val_arst[0], ff.sig_arst, ff.sig_q);
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else
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module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_d, ff.sig_arst, ff.sig_q);
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} else {
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if (ff.pol_arst)
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module->addMux(NEW_ID, ff.sig_d, ff.val_arst, ff.sig_arst, ff.sig_q);
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else
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module->addMux(NEW_ID, ff.val_arst, ff.sig_d, ff.sig_arst, ff.sig_q);
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}
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} else {
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module->connect(ff.sig_q, ff.sig_d);
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}
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did_something = true;
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continue;
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}
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} else if (ff.sig_ce == (ff.pol_ce ? State::S1 : State::S0)) {
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// Always-active enable. Just remove it.
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// For FF, just remove the useless enable.
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log("Removing always-active EN on %s (%s) from module %s.\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_ce = false;
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changed = true;
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}
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}
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if (ff.has_clk) {
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if (ff.sig_clk.is_fully_const()) {
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// Const clock — the D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver).
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// Const clock — the D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver).
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log("Handling const CLK on %s (%s) from module %s (removing D path).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_d = ff.has_en = ff.has_clk = ff.has_srst = false;
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ff.has_ce = ff.has_clk = ff.has_srst = false;
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changed = true;
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}
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}
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if (ff.has_d && ff.sig_d == ff.sig_q) {
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if ((ff.has_clk || ff.has_gclk) && ff.sig_d == ff.sig_q) {
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// Q wrapped back to D, can be removed.
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if (ff.has_clk && ff.has_srst) {
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// FF with sync reset — connect the sync reset to D instead.
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log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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if (ff.has_en && ff.ce_over_srst) {
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if (!ff.pol_en) {
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if (ff.has_ce && ff.ce_over_srst) {
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if (!ff.pol_ce) {
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if (ff.is_fine)
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ff.sig_en = module->NotGate(NEW_ID, ff.sig_en);
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ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce);
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else
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ff.sig_en = module->Not(NEW_ID, ff.sig_en);
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ff.sig_ce = module->Not(NEW_ID, ff.sig_ce);
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}
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if (!ff.pol_srst) {
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if (ff.is_fine)
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@ -527,28 +542,34 @@ struct OptDffWorker
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ff.sig_srst = module->Not(NEW_ID, ff.sig_srst);
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}
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if (ff.is_fine)
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ff.sig_en = module->AndGate(NEW_ID, ff.sig_en, ff.sig_srst);
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ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst);
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else
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ff.sig_en = module->And(NEW_ID, ff.sig_en, ff.sig_srst);
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ff.pol_en = true;
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ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst);
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ff.pol_ce = true;
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} else {
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ff.pol_en = ff.pol_srst;
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ff.sig_en = ff.sig_srst;
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ff.pol_ce = ff.pol_srst;
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ff.sig_ce = ff.sig_srst;
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}
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ff.has_en = true;
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ff.has_ce = true;
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ff.has_srst = false;
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ff.sig_d = ff.val_d = ff.val_srst;
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ff.d_is_const = true;
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ff.sig_d = ff.val_srst;
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changed = true;
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} else {
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// The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver).
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log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_d = ff.has_en = ff.has_clk = false;
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ff.has_clk = ff.has_ce = ff.has_clk = false;
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changed = true;
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}
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}
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if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {
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log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_aload = false;
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changed = true;
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}
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// Now check if any bit can be replaced by a constant.
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pool<int> removed_sigbits;
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for (int i = 0; i < ff.width; i++) {
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@ -565,7 +586,7 @@ struct OptDffWorker
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}
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if (val == State::Sm)
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continue;
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if (ff.has_d) {
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if (ff.has_clk || ff.has_gclk) {
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if (!ff.sig_d[i].wire) {
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val = combine_const(val, ff.sig_d[i].data);
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if (val == State::Sm)
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@ -593,6 +614,34 @@ struct OptDffWorker
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continue;
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}
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}
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if (ff.has_aload) {
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if (!ff.sig_ad[i].wire) {
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val = combine_const(val, ff.sig_ad[i].data);
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if (val == State::Sm)
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continue;
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} else {
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if (!opt.sat)
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continue;
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// For each register bit, try to prove that it cannot change from the initial value. If so, remove it
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if (!modwalker.has_drivers(ff.sig_ad.extract(i)))
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continue;
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if (val != State::S0 && val != State::S1)
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continue;
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int init_sat_pi = qcsat.importSigBit(val);
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int q_sat_pi = qcsat.importSigBit(ff.sig_q[i]);
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int d_sat_pi = qcsat.importSigBit(ff.sig_ad[i]);
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qcsat.prepare();
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// Try to find out whether the register bit can change under some circumstances
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bool counter_example_found = qcsat.ez->solve(qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi)));
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// If the register bit cannot change, we can replace it with a constant
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if (counter_example_found)
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continue;
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}
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}
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log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", val ? 1 : 0,
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i, log_id(cell), log_id(cell->type), log_id(module));
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@ -616,7 +665,7 @@ struct OptDffWorker
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// The cell has been simplified as much as possible already. Now try to spice it up with enables / sync resets.
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if (ff.has_clk) {
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if (!ff.has_arst && !ff.has_sr && (!ff.has_srst || !ff.has_en || ff.ce_over_srst) && !opt.nosdff) {
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if (!ff.has_arst && !ff.has_sr && (!ff.has_srst || !ff.has_ce || ff.ce_over_srst) && !opt.nosdff) {
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// Try to merge sync resets.
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std::map<ctrls_t, std::vector<int>> groups;
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std::vector<int> remaining_indices;
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@ -677,7 +726,7 @@ struct OptDffWorker
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new_ff.has_srst = true;
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new_ff.sig_srst = srst.first;
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new_ff.pol_srst = srst.second;
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if (new_ff.has_en)
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if (new_ff.has_ce)
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new_ff.ce_over_srst = true;
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Cell *new_cell = new_ff.emit(module, NEW_ID);
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if (new_cell)
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@ -695,7 +744,7 @@ struct OptDffWorker
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changed = true;
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}
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}
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if ((!ff.has_srst || !ff.has_en || !ff.ce_over_srst) && !opt.nodffe) {
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if ((!ff.has_srst || !ff.has_ce || !ff.ce_over_srst) && !opt.nodffe) {
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// Try to merge enables.
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std::map<std::pair<patterns_t, ctrls_t>, std::vector<int>> groups;
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std::vector<int> remaining_indices;
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@ -725,8 +774,8 @@ struct OptDffWorker
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if (!opt.simple_dffe)
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patterns = find_muxtree_feedback_patterns(ff.sig_d[i], ff.sig_q[i], pattern_t());
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if (!patterns.empty() || !enables.empty()) {
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if (ff.has_en)
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enables.insert(ctrl_t(ff.sig_en, ff.pol_en));
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if (ff.has_ce)
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enables.insert(ctrl_t(ff.sig_ce, ff.pol_ce));
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simplify_patterns(patterns);
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groups[std::make_pair(patterns, enables)].push_back(i);
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} else
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@ -737,9 +786,9 @@ struct OptDffWorker
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FfData new_ff = ff.slice(it.second);
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ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine);
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new_ff.has_en = true;
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new_ff.sig_en = en.first;
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new_ff.pol_en = en.second;
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new_ff.has_ce = true;
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new_ff.sig_ce = en.first;
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new_ff.pol_ce = en.second;
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new_ff.ce_over_srst = false;
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Cell *new_cell = new_ff.emit(module, NEW_ID);
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if (new_cell)
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