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kernel/ff: Refactor FfData to enable FFs with async load.
- *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
This commit is contained in:
Marcelina Kościelnicka
parent
ec2b5548fe
commit
63b9df8693
10 changed files with 565 additions and 325 deletions
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@ -1398,7 +1398,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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FfData ff(nullptr, cell);
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// $ff / $_FF_ cell: not supported.
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if (ff.has_d && !ff.has_clk && !ff.has_en)
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if (ff.has_gclk)
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return false;
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std::string reg_name = cellname(cell);
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@ -1419,17 +1419,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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for (int i = 0; i < chunks; i++)
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{
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SigSpec sig_d;
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SigSpec sig_d, sig_ad;
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Const val_arst, val_srst;
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std::string reg_bit_name, sig_set_name, sig_clr_name, sig_arst_name;
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std::string reg_bit_name, sig_set_name, sig_clr_name, sig_arst_name, sig_aload_name;
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if (chunky) {
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reg_bit_name = stringf("%s[%d]", reg_name.c_str(), i);
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if (ff.has_d)
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if (ff.has_gclk || ff.has_clk)
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sig_d = ff.sig_d[i];
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if (ff.has_aload)
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sig_ad = ff.sig_ad[i];
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} else {
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reg_bit_name = reg_name;
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if (ff.has_d)
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sig_d = ff.sig_d;
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sig_d = ff.sig_d;
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sig_ad = ff.sig_ad;
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}
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if (ff.has_arst)
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val_arst = chunky ? ff.val_arst[i] : ff.val_arst;
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@ -1437,28 +1439,38 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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val_srst = chunky ? ff.val_srst[i] : ff.val_srst;
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// If there are constants in the sensitivity list, replace them with an intermediate wire
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if (ff.has_sr) {
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if (ff.sig_set[i].wire == NULL)
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{
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sig_set_name = next_auto_id();
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f << stringf("%s" "wire %s = ", indent.c_str(), sig_set_name.c_str());
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dump_const(f, ff.sig_set[i].data);
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f << stringf(";\n");
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}
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if (ff.sig_clr[i].wire == NULL)
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{
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sig_clr_name = next_auto_id();
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f << stringf("%s" "wire %s = ", indent.c_str(), sig_clr_name.c_str());
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dump_const(f, ff.sig_clr[i].data);
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f << stringf(";\n");
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}
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} else if (ff.has_arst) {
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if (ff.sig_arst[i].wire == NULL)
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{
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sig_arst_name = next_auto_id();
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f << stringf("%s" "wire %s = ", indent.c_str(), sig_arst_name.c_str());
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dump_const(f, ff.sig_arst[i].data);
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f << stringf(";\n");
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if (ff.has_clk) {
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if (ff.has_sr) {
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if (ff.sig_set[i].wire == NULL)
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{
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sig_set_name = next_auto_id();
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f << stringf("%s" "wire %s = ", indent.c_str(), sig_set_name.c_str());
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dump_const(f, ff.sig_set[i].data);
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f << stringf(";\n");
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}
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if (ff.sig_clr[i].wire == NULL)
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{
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sig_clr_name = next_auto_id();
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f << stringf("%s" "wire %s = ", indent.c_str(), sig_clr_name.c_str());
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dump_const(f, ff.sig_clr[i].data);
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f << stringf(";\n");
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}
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} else if (ff.has_arst) {
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if (ff.sig_arst[0].wire == NULL)
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{
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sig_arst_name = next_auto_id();
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f << stringf("%s" "wire %s = ", indent.c_str(), sig_arst_name.c_str());
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dump_const(f, ff.sig_arst[0].data);
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f << stringf(";\n");
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}
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} else if (ff.has_aload) {
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if (ff.sig_aload[0].wire == NULL)
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{
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sig_aload_name = next_auto_id();
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f << stringf("%s" "wire %s = ", indent.c_str(), sig_aload_name.c_str());
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dump_const(f, ff.sig_aload[0].data);
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f << stringf(";\n");
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}
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}
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}
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@ -1480,13 +1492,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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f << stringf("%s", sig_clr_name.c_str());
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else
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dump_sigspec(f, ff.sig_clr[i]);
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} else if (ff.has_arst) {
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f << stringf(", %sedge ", ff.pol_arst ? "pos" : "neg");
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if (ff.sig_arst[i].wire == NULL)
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if (ff.sig_arst[0].wire == NULL)
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f << stringf("%s", sig_arst_name.c_str());
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else
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dump_sigspec(f, ff.sig_arst);
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} else if (ff.has_aload) {
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f << stringf(", %sedge ", ff.pol_aload ? "pos" : "neg");
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if (ff.sig_aload[0].wire == NULL)
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f << stringf("%s", sig_aload_name.c_str());
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else
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dump_sigspec(f, ff.sig_aload);
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}
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f << stringf(")\n");
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@ -1507,7 +1524,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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f << stringf("%s" " else ", indent.c_str());
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} else if (ff.has_arst) {
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f << stringf("if (%s", ff.pol_arst ? "" : "!");
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if (ff.sig_arst[i].wire == NULL)
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if (ff.sig_arst[0].wire == NULL)
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f << stringf("%s", sig_arst_name.c_str());
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else
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dump_sigspec(f, ff.sig_arst);
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@ -1515,11 +1532,21 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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dump_sigspec(f, val_arst);
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f << stringf(";\n");
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f << stringf("%s" " else ", indent.c_str());
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} else if (ff.has_aload) {
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f << stringf("if (%s", ff.pol_aload ? "" : "!");
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if (ff.sig_aload[0].wire == NULL)
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f << stringf("%s", sig_aload_name.c_str());
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else
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dump_sigspec(f, ff.sig_aload);
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f << stringf(") %s <= ", reg_bit_name.c_str());
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dump_sigspec(f, sig_ad);
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f << stringf(";\n");
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f << stringf("%s" " else ", indent.c_str());
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}
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if (ff.has_srst && ff.has_en && ff.ce_over_srst) {
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f << stringf("if (%s", ff.pol_en ? "" : "!");
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dump_sigspec(f, ff.sig_en);
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if (ff.has_srst && ff.has_ce && ff.ce_over_srst) {
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f << stringf("if (%s", ff.pol_ce ? "" : "!");
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dump_sigspec(f, ff.sig_ce);
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f << stringf(")\n");
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f << stringf("%s" " if (%s", indent.c_str(), ff.pol_srst ? "" : "!");
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dump_sigspec(f, ff.sig_srst);
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@ -1536,9 +1563,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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f << stringf(";\n");
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f << stringf("%s" " else ", indent.c_str());
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}
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if (ff.has_en) {
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f << stringf("if (%s", ff.pol_en ? "" : "!");
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dump_sigspec(f, ff.sig_en);
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if (ff.has_ce) {
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f << stringf("if (%s", ff.pol_ce ? "" : "!");
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dump_sigspec(f, ff.sig_ce);
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f << stringf(") ");
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}
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}
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@ -1560,7 +1587,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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f << stringf("%s" " else if (%s", indent.c_str(), ff.pol_set ? "" : "!");
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dump_sigspec(f, ff.sig_set[i]);
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f << stringf(") %s = 1'b1;\n", reg_bit_name.c_str());
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if (ff.has_d)
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if (ff.has_aload)
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f << stringf("%s" " else ", indent.c_str());
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} else if (ff.has_arst) {
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f << stringf("if (%s", ff.pol_arst ? "" : "!");
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@ -1568,14 +1595,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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f << stringf(") %s = ", reg_bit_name.c_str());
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dump_sigspec(f, val_arst);
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f << stringf(";\n");
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if (ff.has_d)
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if (ff.has_aload)
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f << stringf("%s" " else ", indent.c_str());
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}
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if (ff.has_d) {
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f << stringf("if (%s", ff.pol_en ? "" : "!");
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dump_sigspec(f, ff.sig_en);
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if (ff.has_aload) {
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f << stringf("if (%s", ff.pol_aload ? "" : "!");
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dump_sigspec(f, ff.sig_aload);
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f << stringf(") %s = ", reg_bit_name.c_str());
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dump_sigspec(f, sig_d);
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dump_sigspec(f, sig_ad);
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f << stringf(";\n");
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}
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}
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