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First draft of Verilog parser support for specify blocks and parameters.

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The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
This commit is contained in:
Udi Finkelstein 2018-03-04 23:35:08 +02:00 • committed by Clifford Wolf
parent f3eaa0ffa5
commit 6378e2cd46
3 changed files with 201 additions and 2 deletions
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3
frontends/verilog/verilog_lexer.l
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@ -145,6 +145,9 @@ YOSYS_NAMESPACE_END
"endfunction" { return TOK_ENDFUNCTION; }
"task" { return TOK_TASK; }
"endtask" { return TOK_ENDTASK; }
"specify" { return TOK_SPECIFY; }
"endspecify" { return TOK_ENDSPECIFY; }
"specparam" { return TOK_SPECPARAM; }
"package" { SV_KEYWORD(TOK_PACKAGE); }
"endpackage" { SV_KEYWORD(TOK_ENDPACKAGE); }
"parameter" { return TOK_PARAMETER; }