mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-26 01:14:37 +00:00
Support for BTOR witness to Yosys witness conversion
This commit is contained in:
Jannis Harder
parent
3e25e61778
commit
636b9f2705
5 changed files with 312 additions and 20 deletions
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@ -28,6 +28,7 @@
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/mem.h"
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#include "kernel/json.h"
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#include <string>
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USING_YOSYS_NAMESPACE
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@ -83,6 +84,20 @@ struct BtorWorker
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vector<string> info_lines;
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dict<int, int> info_clocks;
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struct ywmap_btor_sig {
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SigSpec sig;
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Cell *cell = nullptr;
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ywmap_btor_sig(const SigSpec &sig) : sig(sig) {}
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ywmap_btor_sig(Cell *cell) : cell(cell) {}
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};
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vector<ywmap_btor_sig> ywmap_inputs;
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vector<ywmap_btor_sig> ywmap_states;
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dict<SigBit, int> ywmap_clocks;
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PrettyJson ywmap_json;
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void btorf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
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{
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va_list ap;
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@ -126,6 +141,62 @@ struct BtorWorker
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return " " + infostr;
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}
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template<class T> static std::vector<std::string> witness_path(T *obj) {
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std::vector<std::string> path;
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if (obj->name.isPublic()) {
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auto hdlname = obj->get_string_attribute(ID::hdlname);
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for (auto token : split_tokens(hdlname))
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path.push_back("\\" + token);
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}
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if (path.empty())
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path.push_back(obj->name.str());
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return path;
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}
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void ywmap_state(const SigSpec &sig) {
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if (ywmap_json.active())
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ywmap_states.emplace_back(sig);
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}
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void ywmap_state(Cell *cell) {
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if (ywmap_json.active())
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ywmap_states.emplace_back(cell);
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}
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void ywmap_input(const SigSpec &sig) {
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if (ywmap_json.active())
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ywmap_inputs.emplace_back(sig);
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}
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void emit_ywmap_btor_sig(const ywmap_btor_sig &btor_sig) {
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if (btor_sig.cell == nullptr) {
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if (btor_sig.sig.empty()) {
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ywmap_json.value(nullptr);
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return;
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}
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ywmap_json.begin_array();
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ywmap_json.compact();
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for (auto &chunk : btor_sig.sig.chunks()) {
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log_assert(chunk.is_wire());
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ywmap_json.begin_object();
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ywmap_json.entry("path", witness_path(chunk.wire));
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ywmap_json.entry("width", chunk.width);
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ywmap_json.entry("offset", chunk.offset);
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ywmap_json.end_object();
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}
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ywmap_json.end_array();
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} else {
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ywmap_json.begin_object();
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ywmap_json.compact();
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ywmap_json.entry("path", witness_path(btor_sig.cell));
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Mem *mem = mem_cells[btor_sig.cell];
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ywmap_json.entry("width", mem->width);
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ywmap_json.entry("size", mem->size);
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ywmap_json.end_object();
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}
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}
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void btorf_push(const string &id)
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{
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if (verbose) {
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@ -617,7 +688,7 @@ struct BtorWorker
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SigSpec sig_d = sigmap(cell->getPort(ID::D));
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SigSpec sig_q = sigmap(cell->getPort(ID::Q));
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if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
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if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
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{
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SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C));
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int nid = get_sig_nid(sig_c);
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@ -629,7 +700,11 @@ struct BtorWorker
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if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
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negedge = true;
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info_clocks[nid] |= negedge ? 2 : 1;
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if (!info_filename.empty())
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info_clocks[nid] |= negedge ? 2 : 1;
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if (ywmap_json.active())
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ywmap_clocks[sig_c] |= negedge ? 2 : 1;
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}
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IdString symbol;
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@ -662,6 +737,8 @@ struct BtorWorker
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else
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btorf("%d state %d %s\n", nid, sid, log_id(symbol));
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ywmap_state(sig_q);
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if (nid_init_val >= 0) {
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int nid_init = next_nid++;
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if (verbose)
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@ -683,6 +760,8 @@ struct BtorWorker
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btorf("%d state %d%s\n", nid, sid, getinfo(cell).c_str());
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ywmap_state(sig_y);
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if (cell->type == ID($anyconst)) {
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int nid2 = next_nid++;
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btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
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@ -705,6 +784,8 @@ struct BtorWorker
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btorf("%d state %d%s\n", initstate_nid, sid, getinfo(cell).c_str());
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btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
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btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
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ywmap_state(sig_y);
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}
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add_nid_sig(initstate_nid, sig_y);
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@ -768,6 +849,8 @@ struct BtorWorker
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nid_init_val = next_nid++;
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btorf("%d state %d\n", nid_init_val, sid);
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ywmap_state(nullptr);
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for (int i = 0; i < mem->size; i++) {
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Const thisword = initdata.extract(i*mem->width, mem->width);
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if (thisword.is_fully_undef())
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@ -793,6 +876,8 @@ struct BtorWorker
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else
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btorf("%d state %d %s\n", nid, sid, log_id(mem->memid));
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ywmap_state(cell);
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if (nid_init_val >= 0)
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{
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int nid_init = next_nid++;
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@ -915,10 +1000,13 @@ struct BtorWorker
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int sid = get_bv_sid(GetSize(sig));
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int nid_input = next_nid++;
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if (is_init)
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if (is_init) {
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btorf("%d state %d\n", nid_input, sid);
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else
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ywmap_state(sig);
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} else {
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btorf("%d input %d\n", nid_input, sid);
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ywmap_input(sig);
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}
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int nid_masked_input;
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if (sig_mask_undef.is_fully_ones()) {
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@ -993,6 +1081,7 @@ struct BtorWorker
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int sid = get_bv_sid(GetSize(s));
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int nid = next_nid++;
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btorf("%d input %d\n", nid, sid);
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ywmap_input(s);
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nid_width[nid] = GetSize(s);
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for (int j = 0; j < GetSize(s); j++)
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@ -1075,12 +1164,15 @@ struct BtorWorker
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return nid;
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}
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BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, bool print_internal_names, string info_filename) :
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BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, bool print_internal_names, string info_filename, string ywmap_filename) :
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f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad), cover_mode(cover_mode), print_internal_names(print_internal_names), info_filename(info_filename)
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{
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if (!info_filename.empty())
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infof("name %s\n", log_id(module));
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if (!ywmap_filename.empty())
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ywmap_json.write_to_file(ywmap_filename);
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memories = Mem::get_all_memories(module);
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dict<IdString, Mem*> mem_dict;
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@ -1111,6 +1203,7 @@ struct BtorWorker
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int nid = next_nid++;
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btorf("%d input %d%s\n", nid, sid, getinfo(wire).c_str());
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ywmap_input(wire);
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add_nid_sig(nid, sig);
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if (!info_filename.empty()) {
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@ -1122,6 +1215,16 @@ struct BtorWorker
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info_clocks[nid] |= 2;
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}
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}
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if (ywmap_json.active()) {
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auto gclk_attr = wire->attributes.find(ID::replaced_by_gclk);
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if (gclk_attr != wire->attributes.end()) {
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if (gclk_attr->second == State::S1)
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ywmap_clocks[sig] |= 1;
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else if (gclk_attr->second == State::S0)
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ywmap_clocks[sig] |= 2;
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}
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}
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}
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btorf_pop("inputs");
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@ -1378,6 +1481,42 @@ struct BtorWorker
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f << it;
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f.close();
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}
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if (ywmap_json.active())
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{
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ywmap_json.begin_object();
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ywmap_json.entry("version", "Yosys Witness BTOR map");
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ywmap_json.entry("generator", yosys_version_str);
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ywmap_json.name("clocks");
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ywmap_json.begin_array();
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for (auto &entry : ywmap_clocks) {
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if (entry.second != 1 && entry.second != 2)
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continue;
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log_assert(entry.first.is_wire());
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ywmap_json.begin_object();
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ywmap_json.compact();
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ywmap_json.entry("path", witness_path(entry.first.wire));
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ywmap_json.entry("offset", entry.first.offset);
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ywmap_json.entry("edge", entry.second == 1 ? "posedge" : "negedge");
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ywmap_json.end_object();
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}
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ywmap_json.end_array();
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ywmap_json.name("inputs");
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ywmap_json.begin_array();
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for (auto &entry : ywmap_inputs)
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emit_ywmap_btor_sig(entry);
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ywmap_json.end_array();
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ywmap_json.name("states");
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ywmap_json.begin_array();
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for (auto &entry : ywmap_states)
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emit_ywmap_btor_sig(entry);
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ywmap_json.end_array();
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ywmap_json.end_object();
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}
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}
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};
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@ -1406,11 +1545,15 @@ struct BtorBackend : public Backend {
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log(" -x\n");
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log(" Output symbols for internal netnames (starting with '$')\n");
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log("\n");
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log(" -ywmap <filename>\n");
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log(" Create a map file for conversion to and from Yosys witness traces\n");
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log("\n");
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = false;
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string info_filename;
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string ywmap_filename;
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log_header(design, "Executing BTOR backend.\n");
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@ -1443,6 +1586,10 @@ struct BtorBackend : public Backend {
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print_internal_names = true;
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continue;
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}
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if (args[argidx] == "-ywmap" && argidx+1 < args.size()) {
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ywmap_filename = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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@ -1455,7 +1602,7 @@ struct BtorBackend : public Backend {
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*f << stringf("; BTOR description generated by %s for module %s.\n",
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yosys_version_str, log_id(topmod));
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BtorWorker(*f, topmod, verbose, single_bad, cover_mode, print_internal_names, info_filename);
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BtorWorker(*f, topmod, verbose, single_bad, cover_mode, print_internal_names, info_filename, ywmap_filename);
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*f << stringf("; end of yosys output\n");
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}
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@ -110,6 +110,10 @@ class AigerMap:
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def __init__(self, mapfile):
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data = json.load(mapfile)
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version = data.get("version") if isinstance(data, dict) else {}
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if version != "Yosys Witness Aiger map":
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raise click.ClickException(f"{mapfile.name}: unexpected file format version {version!r}")
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self.latch_count = data["latch_count"]
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self.input_count = data["input_count"]
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@ -250,5 +254,132 @@ def yw2aiw(input, mapfile, output):
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click.echo(f"Converted {len(inyw)} time steps.")
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class BtorMap:
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def __init__(self, mapfile):
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self.data = data = json.load(mapfile)
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version = data.get("version") if isinstance(data, dict) else {}
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if version != "Yosys Witness BTOR map":
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raise click.ClickException(f"{mapfile.name}: unexpected file format version {version!r}")
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self.sigmap = WitnessSigMap()
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for mode in ("states", "inputs"):
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for btor_signal_def in data[mode]:
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if btor_signal_def is None:
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continue
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if isinstance(btor_signal_def, dict):
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btor_signal_def["path"] = tuple(btor_signal_def["path"])
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else:
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for chunk in btor_signal_def:
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chunk["path"] = tuple(chunk["path"])
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@cli.command(help="""
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Convert a BTOR witness trace into a Yosys witness trace.
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This requires a Yosys witness BTOR map file as generated by 'write_btor -ywmap'.
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""")
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@click.argument("input", type=click.File("r"))
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@click.argument("mapfile", type=click.File("r"))
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@click.argument("output", type=click.File("w"))
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def wit2yw(input, mapfile, output):
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input_name = input.name
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click.echo(f"Converting BTOR witness trace {input_name!r} to Yosys witness trace {output.name!r}...")
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click.echo(f"Using Yosys witness BTOR map file {mapfile.name!r}")
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btor_map = BtorMap(mapfile)
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input = filter(None, (line.split(';', 1)[0].strip() for line in input))
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sat = next(input, None)
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if sat != "sat":
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raise click.ClickException(f"{input_name}: not a BTOR witness file")
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props = next(input, None)
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t = -1
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line = next(input, None)
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frames = []
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bits = {}
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while line and not line.startswith('.'):
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current_t = int(line[1:].strip())
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if line[0] == '#':
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mode = "states"
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elif line[0] == '@':
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mode = "inputs"
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else:
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raise click.ClickException(f"{input_name}: unexpected data in BTOR witness file")
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if current_t > t:
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t = current_t
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values = WitnessValues()
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frames.append(values)
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line = next(input, None)
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while line and line[0] not in "#@.":
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if current_t > 0 and mode == "states":
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line = next(input, None)
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continue
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tokens = line.split()
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line = next(input, None)
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btor_sig = btor_map.data[mode][int(tokens[0])]
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if btor_sig is None:
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continue
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if isinstance(btor_sig, dict):
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addr = tokens[1]
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if not addr.startswith('[') or not addr.endswith(']'):
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raise click.ClickException(f"{input_name}: expected address in BTOR witness file")
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addr = int(addr[1:-1], 2)
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if addr < 0 or addr >= btor_sig["size"]:
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raise click.ClickException(f"{input_name}: out of bounds address in BTOR witness file")
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btor_sig = [{
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"path": (*btor_sig["path"], f"\\[{addr}]"),
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"width": btor_sig["width"],
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"offset": 0,
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}]
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signal_value = iter(reversed(tokens[2]))
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else:
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signal_value = iter(reversed(tokens[1]))
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for chunk in btor_sig:
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offset = chunk["offset"]
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path = chunk["path"]
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for i in range(offset, offset + chunk["width"]):
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key = (path, i)
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bits[key] = mode == "inputs"
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values[key] = next(signal_value)
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if next(signal_value, None) is not None:
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raise click.ClickException(f"{input_name}: excess bits in BTOR witness file")
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if line is None:
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raise click.ClickException(f"{input_name}: unexpected end of BTOR witness file")
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if line.strip() != '.':
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raise click.ClickException(f"{input_name}: unexpected data in BTOR witness file")
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if next(input, None) is not None:
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raise click.ClickException(f"{input_name}: unexpected trailing data in BTOR witness file")
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outyw = WriteWitness(output, 'yosys-witness wit2yw')
|
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|
||||
outyw.signals = coalesce_signals((), bits)
|
||||
for clock in btor_map.data["clocks"]:
|
||||
outyw.add_clock(clock["path"], clock["offset"], clock["edge"])
|
||||
|
||||
for values in frames:
|
||||
outyw.step(values)
|
||||
|
||||
outyw.end_trace()
|
||||
click.echo(f"Converted {outyw.t} time steps.")
|
||||
|
||||
if __name__ == "__main__":
|
||||
cli()
|
||||
|
|
|
|||
|
|
@ -175,8 +175,9 @@ class WitnessSig:
|
|||
return self.sort_key < other.sort_key
|
||||
|
||||
|
||||
def coalesce_signals(signals):
|
||||
bits = {}
|
||||
def coalesce_signals(signals, bits=None):
|
||||
if bits is None:
|
||||
bits = {}
|
||||
for sig in signals:
|
||||
for bit in sig.bits():
|
||||
if sig.init_only:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue