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Renamed temp module generated by "abc" pass from "logic" to "netlist"

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Clifford Wolf 2013-11-19 01:03:57 +01:00
parent c5e26f839c
commit 63285b300c
2 changed files with 6 additions and 6 deletions
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2
passes/abc/blifparse.cc
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@ -53,7 +53,7 @@ RTLIL::Design *abc_parse_blif(FILE *f)
RTLIL::State lut_default_state = RTLIL::State::Sx;
int port_count = 0;
module->name = "\\logic";
module->name = "\\netlist";
design->modules[module->name] = module;
char buffer[4096];