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Added support for complex set-reset flip-flops in proc_dff

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Clifford Wolf 2013-10-24 16:54:05 +02:00
parent e679a5d046
commit 628b994cf6
3 changed files with 147 additions and 17 deletions
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38
tests/simple/dff_different_styles.v
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@ -65,6 +65,10 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
end
endmodule
// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of
// simulation-implementation mismatches. The following testcases try to cover the
// part that is defined and avoid the undefined cases.
module dffsr1(clk, arst, d, q);
input clk, arst, d;
output reg q;
@ -76,16 +80,26 @@ always @(posedge clk, posedge arst) begin
end
endmodule
// module dffsr2(clk, preset, clear, d, q);
// input clk, preset, clear, d;
// output reg q;
// always @(posedge clk, posedge preset, posedge clear) begin
// if (preset)
// q <= 1;
// else if (clear)
// q <= 0;
// else
// q <= d;
// end
// endmodule
module dffsr2(clk, preset, clear, d, q);
input clk, preset, clear, d;
output q;
(* gentb_clock *)
wire clk, preset, clear, d;
dffsr2_sub uut (clk, preset && !clear, !preset && clear, d, q);
endmodule
(* gentb_skip *)
module dffsr2_sub(clk, preset, clear, d, q);
input clk, preset, clear, d;
output reg q;
always @(posedge clk, posedge preset, posedge clear) begin
if (preset)
q <= 1;
else if (clear)
q <= 0;
else
q <= d;
end
endmodule