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verilog_backend: dump attributes on SwitchRule.

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This appears to be an omission.
This commit is contained in:
whitequark 2019-07-08 15:11:29 +00:00
parent 48655dfb8b
commit 628437b01c
1 changed files with 1 additions and 0 deletions
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1
backends/verilog/verilog_backend.cc
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@ -1494,6 +1494,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
return; return;
} }
dump_attributes(f, indent, sw->attributes);
f << stringf("%s" "casez (", indent.c_str()); f << stringf("%s" "casez (", indent.c_str());
dump_sigspec(f, sw->signal); dump_sigspec(f, sw->signal);
f << stringf(")\n"); f << stringf(")\n");