mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Add read_verilog $changed support

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Dan Gisselquist 2018-10-01 19:41:35 +02:00 • committed by Clifford Wolf
parent 4d2917447c
commit 62424ef3de
1 changed files with 4 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

5
frontends/ast/simplify.cc
View file

@ -1836,7 +1836,7 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode; goto apply_newNode;
} }
if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell") if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed")
{ {
if (GetSize(children) != 1) if (GetSize(children) != 1)
log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
@ -1853,6 +1853,9 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "\\$stable") if (str == "\\$stable")
newNode = new AstNode(AST_EQ, past, present); newNode = new AstNode(AST_EQ, past, present);
else if (str == "\\$changed")
newNode = new AstNode(AST_NE, past, present);
else if (str == "\\$rose") else if (str == "\\$rose")
newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present); newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present);