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intel_alm: increase abc9 -W

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Dan Ravensloft 2020-07-26 19:11:55 +01:00 • committed by Marcelina Kościelnicka
parent 9bcde4d82b
commit 62311b7ec0
2 changed files with 7 additions and 7 deletions
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12
tests/arch/intel_alm/mux.ys
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@ -47,9 +47,9 @@ proc
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 3 t:MISTRAL_ALUT5
select -assert-count 1 t:MISTRAL_ALUT6
select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
select -assert-count 1 t:MISTRAL_ALUT3
select -assert-count 2 t:MISTRAL_ALUT6
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
design -load read
@ -69,9 +69,9 @@ proc
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 2 t:MISTRAL_ALUT5
select -assert-count 4 t:MISTRAL_ALUT6
select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
select -assert-count 1 t:MISTRAL_ALUT3
select -assert-count 5 t:MISTRAL_ALUT6
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
design -load read