Himbaechel for Xilinx uarch : Improve mapping of multiplexers

- Add explicitly handling of A_WIDTH=1 for completeness
- mux2 uses one LUT3 instead of a hard mux (which did use LUTs anyway)
- mux4 uses one LUT4 instead of hard muxes (which did use LUTs anyway)
- mux8 uses only bottom half of a slice
- Add a mux12 for intermediate variant between mux8 and mux16
- For sizes larger than 16 inputs, instantiate the right mux size
- More comments about implementation choices
- More tests including with -widemux and -abc9, and more comments

tests/arch/common/mux.v

@@ -51,10 +51,32 @@ module mux8 ( S, D, Y );
     end
 endmodule
 
+module mux12 (D, S, Y);
+    input  [11:0] D;
+    input  [3:0] S;
+    output Y;
+
+    wire[15:0] D16;
+
+    assign D16 = {4'bx, D};
+    assign Y = D16[S];
+endmodule
+
 module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
+    input  [15:0] D;
+    input  [3:0] S;
+    output Y;
 
     assign Y = D[S];
 endmodule
+
+module mux20 (D, S, Y);
+    input  [19:0] D;
+    input  [4:0] S;
+    output Y;
+
+    wire[31:0] D32;
+
+    assign D32 = {12'bx, D};
+    assign Y = D32[S];
+endmodule