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Himbaechel for Xilinx uarch : Improve mapping of multiplexers
- Add explicitly handling of A_WIDTH=1 for completeness - mux2 uses one LUT3 instead of a hard mux (which did use LUTs anyway) - mux4 uses one LUT4 instead of hard muxes (which did use LUTs anyway) - mux8 uses only bottom half of a slice - Add a mux12 for intermediate variant between mux8 and mux16 - For sizes larger than 16 inputs, instantiate the right mux size - More comments about implementation choices - More tests including with -widemux and -abc9, and more comments
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Adrien Prost-Boucle
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62196cbc0a
3 changed files with 176 additions and 36 deletions
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@ -51,10 +51,32 @@ module mux8 ( S, D, Y );
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end
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endmodule
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module mux12 (D, S, Y);
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input [11:0] D;
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input [3:0] S;
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output Y;
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wire[15:0] D16;
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assign D16 = {4'bx, D};
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assign Y = D16[S];
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endmodule
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module mux16 (D, S, Y);
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input [15:0] D;
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input [3:0] S;
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output Y;
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input [15:0] D;
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input [3:0] S;
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output Y;
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assign Y = D[S];
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endmodule
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module mux20 (D, S, Y);
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input [19:0] D;
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input [4:0] S;
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output Y;
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wire[31:0] D32;
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assign D32 = {12'bx, D};
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assign Y = D32[S];
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endmodule
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@ -1,6 +1,10 @@
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read_verilog ../common/mux.v
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design -save read
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# mux2
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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@ -8,9 +12,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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# Ensure there are no other cells
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select -assert-none t:LUT3 %% t:* %D
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# mux4
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design -load read
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hierarchy -top mux4
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proc
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@ -19,9 +26,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT6
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# Ensure there are no other cells
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select -assert-none t:LUT6 %% t:* %D
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# mux8 without widemux
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design -load read
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hierarchy -top mux8
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proc
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@ -31,9 +41,43 @@ cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 2 t:LUT6
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# Ensure there are no other cells
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select -assert-none t:LUT3 t:LUT6 %% t:* %D
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# mux8 with widemux 5
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad -widemux 5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT6
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select -assert-count 1 t:MUXF7
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# Ensure there are no other cells
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select -assert-none t:LUT6 t:MUXF7 %% t:* %D
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# mux12 with widemux 5
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# There is no equivalence check because selection values 12 to 15 are unspecified
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design -load read
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hierarchy -top mux12
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proc
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synth_xilinx -noiopad -widemux 5
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cd mux12 # Constrain all select calls below inside the top module
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select -assert-count 3 t:LUT6
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select -assert-max 2 t:MUXF7
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select -assert-count 1 t:MUXF8
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# Ensure there are no other cells
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select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
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# mux16 without widemux
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design -load read
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hierarchy -top mux16
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proc
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@ -47,4 +91,45 @@ select -assert-max 7 t:LUT6
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select -assert-max 2 t:MUXF7
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dump
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# Ensure there are no other cells
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select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D
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# mux16 with widemux 5
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad -widemux 5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 4 t:LUT6
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select -assert-count 2 t:MUXF7
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select -assert-count 1 t:MUXF8
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dump
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# Ensure there are no other cells
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select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
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# mux20 with widemux 5
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# Expect one mux16 (4 lut6 + 2 muxf7 + muxf8) + one mux4 (one lut6), then one mux2 (one lut3)
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# These mapping results are achieved only with abc9 (without abc, we get undesired additional muxf7/muxf8)
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# There is no equivalence check because selection values 20 to 31 are unspecified
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design -load read
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hierarchy -top mux20
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proc
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scratchpad -set abc9.D 5000 # Set a period high enough so we get area-optimized result
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synth_xilinx -noiopad -widemux 5 -abc9
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cd mux20 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 5 t:LUT6
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select -assert-count 2 t:MUXF7
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select -assert-count 1 t:MUXF8
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dump
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# Ensure there are no other cells
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select -assert-none t:LUT3 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
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