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Add latch test modified from #1363

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Eddie Hung 2019-09-27 12:50:20 -07:00 • committed by Marcin Kościelnicki
parent 5b5756b91e
commit 6216e45eda
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tests/xilinx/latches.ys Normal file
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read_verilog latches.v
proc
flatten
equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
async2sync
equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load preopt
synth_xilinx
cd top
select -assert-count 1 t:LUT1
select -assert-count 2 t:LUT3
select -assert-count 3 t:LDCE
select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D