mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-03 16:48:07 +00:00
Code Activity

Add latch test modified from #1363

Browse source
This commit is contained in:
Eddie Hung 2019-09-27 12:50:20 -07:00 • committed by Marcin Kościelnicki
parent 5b5756b91e
commit 6216e45eda
2 changed files with 73 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

15
tests/xilinx/latches.ys Normal file
View file

@ -0,0 +1,15 @@
read_verilog latches.v
proc
flatten
equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
async2sync
equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load preopt
synth_xilinx
cd top
select -assert-count 1 t:LUT1
select -assert-count 2 t:LUT3
select -assert-count 3 t:LDCE
select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D