mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-12-13 23:26:25 +00:00
Code Activity

verilog: test cases that look like SVA labels #862

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-09-05 12:34:38 +02:00
parent c30fd46ea3
commit 62120bda06
1 changed files with 10 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

10
tests/verilog/sva-in-case-expr.ys Normal file
View file

@ -0,0 +1,10 @@
read_verilog -sv <<EOT
module test(input wire A);
localparam TEST = 1;
always_comb begin
case (A)
TEST: assert(1);
endcase
end
endmodule
EOT