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verilog: test cases that look like SVA labels #862

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Emil J. Tywoniak 2025-09-05 12:34:38 +02:00
parent c30fd46ea3
commit 62120bda06
1 changed files with 10 additions and 0 deletions
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tests/verilog/sva-in-case-expr.ys Normal file
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read_verilog -sv <<EOT
module test(input wire A);
localparam TEST = 1;
always_comb begin
case (A)
TEST: assert(1);
endcase
end
endmodule
EOT