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Clean up some whitepsace outliers

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This commit is contained in:
Larry Doolittle 2019-02-24 22:08:52 -08:00 • committed by Clifford Wolf
parent c258b99040
commit 61fc411c5d
3 changed files with 6 additions and 6 deletions
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4
passes/techmap/dfflibmap.cc
View file

@ -660,8 +660,8 @@ struct DfflibmapPass : public Pass {
map_adff_to_dff("$_DFF_PP0_", "$_DFF_P_"); map_adff_to_dff("$_DFF_PP0_", "$_DFF_P_");
map_adff_to_dff("$_DFF_PP1_", "$_DFF_P_"); map_adff_to_dff("$_DFF_PP1_", "$_DFF_P_");
log(" final dff cell mappings:\n"); log(" final dff cell mappings:\n");
logmap_all(); logmap_all();
for (auto &it : design->modules_) for (auto &it : design->modules_)
if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox")) if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))

4
passes/techmap/flowmap.cc
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@ -132,9 +132,9 @@ static void dump_dot_graph(string filename,
pool<RTLIL::SigBit> nodes, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges, pool<RTLIL::SigBit> nodes, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges,
pool<RTLIL::SigBit> inputs, pool<RTLIL::SigBit> outputs, pool<RTLIL::SigBit> inputs, pool<RTLIL::SigBit> outputs,
std::function<GraphStyle(RTLIL::SigBit)> node_style = std::function<GraphStyle(RTLIL::SigBit)> node_style =
[](RTLIL::SigBit) { return GraphStyle{}; }, [](RTLIL::SigBit) { return GraphStyle{}; },
std::function<GraphStyle(RTLIL::SigBit, RTLIL::SigBit)> edge_style = std::function<GraphStyle(RTLIL::SigBit, RTLIL::SigBit)> edge_style =
[](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; }, [](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
string name = "") string name = "")
{ {
FILE *f = fopen(filename.c_str(), "w"); FILE *f = fopen(filename.c_str(), "w");

4
techlibs/ecp5/cells_sim.v
View file

@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 (
input RAD0, RAD1, RAD2, RAD3, input RAD0, RAD1, RAD2, RAD3,
output DO0, DO1 output DO0, DO1
); );
parameter WCKMUX = "WCK"; parameter WCKMUX = "WCK";
parameter WREMUX = "WRE"; parameter WREMUX = "WRE";
parameter INITVAL_0 = 16'h0000; parameter INITVAL_0 = 16'h0000;
parameter INITVAL_1 = 16'h0000; parameter INITVAL_1 = 16'h0000;
@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 (
input [3:0] RAD, input [3:0] RAD,
output [3:0] DO output [3:0] DO
); );
parameter WCKMUX = "WCK"; parameter WCKMUX = "WCK";
parameter WREMUX = "WRE"; parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000; parameter [63:0] INITVAL = 64'h0000000000000000;