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Added Yosys Manual

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Clifford Wolf 2013-07-20 15:19:12 +02:00
parent 3650fd7fbe
commit 61ed6b32d1
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manual/FILES_StateOfTheArt/arrays01.v Normal file
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module uut_arrays01(clock, we, addr, wr_data, rd_data);
input clock, we;
input [3:0] addr, wr_data;
output [3:0] rd_data;
reg [3:0] rd_data;
reg [3:0] memory [15:0];
always @(posedge clock) begin
if (we)
memory[addr] <= wr_data;
rd_data <= memory[addr];
end
endmodule