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Added Yosys Manual

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Clifford Wolf 2013-07-20 15:19:12 +02:00
parent 3650fd7fbe
commit 61ed6b32d1
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manual/FILES_StateOfTheArt/always01.v Normal file
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module uut_always01(clock, reset, c3, c2, c1, c0);
input clock, reset;
output c3, c2, c1, c0;
reg [3:0] count;
assign {c3, c2, c1, c0} = count;
always @(posedge clock)
count <= reset ? 0 : count + 1;
endmodule