mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 03:57:52 +00:00
Code Activity

Update tests

Browse source
This commit is contained in:
Miodrag Milanovic 2023-03-18 18:12:02 +01:00 • committed by myrtle
parent ff9f1fb86e
commit 61da330a38
7 changed files with 16 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

8
tests/arch/machxo2/mux.ys
View file

@ -7,7 +7,7 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux4
@ -17,7 +17,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux8
@ -27,7 +27,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux16
@ -37,4 +37,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D