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Update tests
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7 changed files with 16 additions and 16 deletions
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@ -7,7 +7,7 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT4
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select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
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select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
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design -load read
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hierarchy -top mux4
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@ -17,7 +17,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT4
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select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
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select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
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design -load read
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hierarchy -top mux8
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@ -27,7 +27,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 5 t:LUT4
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select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
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select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
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design -load read
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hierarchy -top mux16
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@ -37,4 +37,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-max 12 t:LUT4
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select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
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select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
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