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look at all those chickens
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15 changed files with 48 additions and 42 deletions
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@ -343,9 +343,9 @@ private:
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//recurse to GLIFT model the child module. However, we need to augment the ports list
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//with taint signals and connect the new ports to the corresponding taint signals.
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RTLIL::Module *cell_module_def = module->design->module(cell->type);
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dict<RTLIL::IdString, RTLIL::SigSpec> orig_ports = cell->connections();
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auto orig_ports = cell->connections();
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log("Adding cell %s\n", cell_module_def->name.c_str());
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for (auto &it : orig_ports) {
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for (auto &&it : orig_ports) {
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RTLIL::SigSpec port = it.second;
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RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port);
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