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look at all those chickens

This commit is contained in:
Emil J. Tywoniak 2024-06-13 14:27:11 +02:00
parent 8bdcc6987b
commit 61cf4b6fb6
15 changed files with 48 additions and 42 deletions

View file

@ -343,9 +343,9 @@ private:
//recurse to GLIFT model the child module. However, we need to augment the ports list
//with taint signals and connect the new ports to the corresponding taint signals.
RTLIL::Module *cell_module_def = module->design->module(cell->type);
dict<RTLIL::IdString, RTLIL::SigSpec> orig_ports = cell->connections();
auto orig_ports = cell->connections();
log("Adding cell %s\n", cell_module_def->name.c_str());
for (auto &it : orig_ports) {
for (auto &&it : orig_ports) {
RTLIL::SigSpec port = it.second;
RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port);