3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-01 17:03:19 +00:00

look at all those chickens

This commit is contained in:
Emil J. Tywoniak 2024-06-13 14:27:11 +02:00
parent 8bdcc6987b
commit 61cf4b6fb6
15 changed files with 48 additions and 42 deletions

View file

@ -33,7 +33,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
for (auto cell : module->cells())
for (auto &port : cell->connections_)
for (auto &&port : cell->connections_)
if (ct.cell_output(cell->type, port.first))
sigmap(port.second).replace(sig, dummy_wire, &port.second);