look at all those chickens

passes/cmds/connect.cc

@@ -33,7 +33,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
 
 	for (auto cell : module->cells())
-	for (auto &port : cell->connections_)
+	for (auto &&port : cell->connections_)
 		if (ct.cell_output(cell->type, port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
 

passes/cmds/connwrappers.cc

@@ -105,7 +105,7 @@ struct ConnwrappersWorker
 
 		for (auto cell : module->selected_cells())
 		{
-			for (auto &conn : cell->connections_)
+			for (auto &&conn : cell->connections_)
 			{
 				std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
 				RTLIL::SigSpec old_sig;

passes/cmds/glift.cc

@@ -343,9 +343,9 @@ private:
 				//recurse to GLIFT model the child module. However, we need to augment the ports list
 				//with taint signals and connect the new ports to the corresponding taint signals.
 				RTLIL::Module *cell_module_def = module->design->module(cell->type);
-				dict<RTLIL::IdString, RTLIL::SigSpec> orig_ports = cell->connections();
+				auto orig_ports = cell->connections();
 				log("Adding cell %s\n", cell_module_def->name.c_str());
-				for (auto &it : orig_ports) {
+				for (auto &&it : orig_ports) {
 					RTLIL::SigSpec port = it.second;
 					RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port);
 

passes/cmds/select.cc

@@ -106,7 +106,8 @@ static bool match_attr_val(const RTLIL::Const &value, const std::string &pattern
 	log_abort();
 }
 
-static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, const std::string &name_pat, const std::string &value_pat, char match_op)
+template <typename SmellsLikeDict>
+static bool match_attr(const SmellsLikeDict &attributes, const std::string &name_pat, const std::string &value_pat, char match_op)
 {
 	if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
 		for (auto &it : attributes) {
@@ -124,7 +125,8 @@ static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, co
 	return false;
 }
 
-static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, const std::string &match_expr)
+template <typename SmellsLikeDict>
+static bool match_attr(const SmellsLikeDict &attributes, const std::string &match_expr)
 {
 	size_t pos = match_expr.find_first_of("<!=>");
 

passes/cmds/setattr.cc

@@ -45,7 +45,8 @@ struct setunset_t
 	}
 };
 
-static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, const std::vector<setunset_t> &list)
+template <typename SmellsLikeDict>
+static void do_setunset(SmellsLikeDict &attrs, const std::vector<setunset_t> &list)
 {
 	for (auto &item : list)
 		if (item.unset)

passes/cmds/setundef.cc

@@ -245,7 +245,7 @@ struct SetundefPass : public Pass {
 			if (params_mode)
 			{
 				for (auto *cell : module->selected_cells()) {
-					for (auto &parameter : cell->parameters) {
+					for (auto &&parameter : cell->parameters) {
 						for (auto &bit : parameter.second.bits) {
 							if (bit > RTLIL::State::S1)
 								bit = worker.next_bit();

passes/cmds/splice.cc

@@ -188,7 +188,7 @@ struct SpliceWorker
 		for (auto cell : mod_cells) {
 			if (!sel_by_wire && !design->selected(module, cell))
 				continue;
-			for (auto &conn : cell->connections_)
+			for (auto &&conn : cell->connections_)
 				if (ct.cell_input(cell->type, conn.first)) {
 					if (ports.size() > 0 && !ports.count(conn.first))
 						continue;

passes/hierarchy/hierarchy.cc

@@ -574,7 +574,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 
 		RTLIL::Module *mod = design->module(cell->type);
 
-		for (auto &conn : cell->connections_) {
+		for (auto &&conn : cell->connections_) {
 			int conn_size = conn.second.size();
 			RTLIL::IdString portname = conn.first;
 			if (portname.begins_with("$")) {

passes/sat/expose.cc

@@ -498,7 +498,7 @@ struct ExposePass : public Pass {
 				for (auto cell : module->cells()) {
 					if (!ct.cell_known(cell->type))
 						continue;
-					for (auto &conn : cell->connections_)
+					for (auto &&conn : cell->connections_)
 						if (ct.cell_output(cell->type, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}
@@ -519,7 +519,7 @@ struct ExposePass : public Pass {
 				for (auto cell : module->cells()) {
 					if (!ct.cell_known(cell->type))
 						continue;
-					for (auto &conn : cell->connections_)
+					for (auto &&conn : cell->connections_)
 						if (ct.cell_input(cell->type, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}