From 8566489d8510af1e3086af9b692490f35db377a8 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Fri, 9 Feb 2024 23:51:00 +0000 Subject: [PATCH 1/4] stat: Add sequential area output to stat -liberty Checks to see if a cell is of type ff in the liberty, and keeps track of an additional area value. ``` Chip area for module '\addr': 92.280720 Sequential area for module '\addr': 38.814720 ``` Signed-off-by: Ethan Mahintorabi --- passes/cmds/stat.cc | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index d34373c1c..9849d2537 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -28,6 +28,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +struct cell_data_t { + double area; + bool is_flip_flop; +}; + struct statdata_t { #define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \ @@ -39,6 +44,7 @@ struct statdata_t STAT_INT_MEMBERS #undef X double area; + double sequential_area; string tech; std::map techinfo; @@ -74,7 +80,7 @@ struct statdata_t #undef X } - statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict &cell_area, string techname) + statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict &cell_properties, string techname) { tech = techname; @@ -131,11 +137,17 @@ struct statdata_t cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q))); } - if (!cell_area.empty()) { - if (cell_area.count(cell_type)) - area += cell_area.at(cell_type); - else + if (!cell_properties.empty()) { + if (cell_properties.count(cell_type)) { + cell_data_t cell_data = cell_properties.at(cell_type); + if (cell_data.is_flip_flop) { + sequential_area += cell_data.area; + } + area += cell_data.area; + } + else { unknown_cell_area.insert(cell_type); + } } num_cells++; @@ -244,6 +256,7 @@ struct statdata_t if (area != 0) { log("\n"); log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area); + log(" Sequential area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), sequential_area); } if (tech == "xilinx") @@ -325,7 +338,7 @@ statdata_t hierarchy_worker(std::map &mod_stat, RTL return mod_data; } -void read_liberty_cellarea(dict &cell_area, string liberty_file) +void read_liberty_cellarea(dict &cell_properties, string liberty_file) { std::ifstream f; f.open(liberty_file.c_str()); @@ -341,8 +354,9 @@ void read_liberty_cellarea(dict &cell_area, string liberty_fil continue; LibertyAst *ar = cell->find("area"); + bool is_flip_flop = cell->find("ff") != nullptr; if (ar != nullptr && !ar->value.empty()) - cell_area["\\" + cell->args[0]] = atof(ar->value.c_str()); + cell_properties["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop}; } } @@ -383,7 +397,7 @@ struct StatPass : public Pass { bool width_mode = false, json_mode = false; RTLIL::Module *top_mod = nullptr; std::map mod_stat; - dict cell_area; + dict cell_properties; string techname; size_t argidx; @@ -396,7 +410,7 @@ struct StatPass : public Pass { if (args[argidx] == "-liberty" && argidx+1 < args.size()) { string liberty_file = args[++argidx]; rewrite_filename(liberty_file); - read_liberty_cellarea(cell_area, liberty_file); + read_liberty_cellarea(cell_properties, liberty_file); continue; } if (args[argidx] == "-tech" && argidx+1 < args.size()) { @@ -439,7 +453,7 @@ struct StatPass : public Pass { if (mod->get_bool_attribute(ID::top)) top_mod = mod; - statdata_t data(design, mod, width_mode, cell_area, techname); + statdata_t data(design, mod, width_mode, cell_properties, techname); mod_stat[mod->name] = data; if (json_mode) { From 2d8343d4234da07e026225682694e4192db75c3a Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Thu, 15 Feb 2024 23:59:19 +0000 Subject: [PATCH 2/4] update type and variable names Signed-off-by: Ethan Mahintorabi --- passes/cmds/stat.cc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 9849d2537..82ad80779 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -28,9 +28,9 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct cell_data_t { +struct cell_area_t { double area; - bool is_flip_flop; + bool is_sequential; }; struct statdata_t @@ -80,7 +80,7 @@ struct statdata_t #undef X } - statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict &cell_properties, string techname) + statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict &cell_properties, string techname) { tech = techname; @@ -139,8 +139,8 @@ struct statdata_t if (!cell_properties.empty()) { if (cell_properties.count(cell_type)) { - cell_data_t cell_data = cell_properties.at(cell_type); - if (cell_data.is_flip_flop) { + cell_area_t cell_data = cell_properties.at(cell_type); + if (cell_data.is_sequential) { sequential_area += cell_data.area; } area += cell_data.area; @@ -338,7 +338,7 @@ statdata_t hierarchy_worker(std::map &mod_stat, RTL return mod_data; } -void read_liberty_cellarea(dict &cell_properties, string liberty_file) +void read_liberty_cellarea(dict &cell_properties, string liberty_file) { std::ifstream f; f.open(liberty_file.c_str()); @@ -397,7 +397,7 @@ struct StatPass : public Pass { bool width_mode = false, json_mode = false; RTLIL::Module *top_mod = nullptr; std::map mod_stat; - dict cell_properties; + dict cell_properties; string techname; size_t argidx; From f0df0e3912bdc40075a2762530d21add11c7e6d0 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Fri, 16 Feb 2024 00:01:44 +0000 Subject: [PATCH 3/4] update type and variable names Signed-off-by: Ethan Mahintorabi --- passes/cmds/stat.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 82ad80779..c74aa7c14 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -80,7 +80,7 @@ struct statdata_t #undef X } - statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict &cell_properties, string techname) + statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict &cell_area, string techname) { tech = techname; @@ -137,9 +137,9 @@ struct statdata_t cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q))); } - if (!cell_properties.empty()) { - if (cell_properties.count(cell_type)) { - cell_area_t cell_data = cell_properties.at(cell_type); + if (!cell_area.empty()) { + if (cell_area.count(cell_type)) { + cell_area_t cell_data = cell_area.at(cell_type); if (cell_data.is_sequential) { sequential_area += cell_data.area; } @@ -338,7 +338,7 @@ statdata_t hierarchy_worker(std::map &mod_stat, RTL return mod_data; } -void read_liberty_cellarea(dict &cell_properties, string liberty_file) +void read_liberty_cellarea(dict &cell_area, string liberty_file) { std::ifstream f; f.open(liberty_file.c_str()); @@ -356,7 +356,7 @@ void read_liberty_cellarea(dict &cell_properties, string LibertyAst *ar = cell->find("area"); bool is_flip_flop = cell->find("ff") != nullptr; if (ar != nullptr && !ar->value.empty()) - cell_properties["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop}; + cell_area["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop}; } } @@ -397,7 +397,7 @@ struct StatPass : public Pass { bool width_mode = false, json_mode = false; RTLIL::Module *top_mod = nullptr; std::map mod_stat; - dict cell_properties; + dict cell_area; string techname; size_t argidx; @@ -410,7 +410,7 @@ struct StatPass : public Pass { if (args[argidx] == "-liberty" && argidx+1 < args.size()) { string liberty_file = args[++argidx]; rewrite_filename(liberty_file); - read_liberty_cellarea(cell_properties, liberty_file); + read_liberty_cellarea(cell_area, liberty_file); continue; } if (args[argidx] == "-tech" && argidx+1 < args.size()) { @@ -453,7 +453,7 @@ struct StatPass : public Pass { if (mod->get_bool_attribute(ID::top)) top_mod = mod; - statdata_t data(design, mod, width_mode, cell_properties, techname); + statdata_t data(design, mod, width_mode, cell_area, techname); mod_stat[mod->name] = data; if (json_mode) { From b8a1009de98406d6841357954724807bd034176e Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Fri, 16 Feb 2024 07:44:09 -0800 Subject: [PATCH 4/4] Update passes/cmds/stat.cc Make reporting line more clear about the non cumulative area of sequential cells Co-authored-by: N. Engelhardt --- passes/cmds/stat.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index c74aa7c14..85107b68f 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -256,7 +256,7 @@ struct statdata_t if (area != 0) { log("\n"); log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area); - log(" Sequential area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), sequential_area); + log(" of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0*sequential_area/area); } if (tech == "xilinx")