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https://github.com/YosysHQ/yosys
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Reduced complexity: NxM -> N log(M)
This commit is contained in:
Alain Dargelas
parent
ad48ce3da5
commit
61b37bebb6
1 changed files with 95 additions and 89 deletions
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@ -15,6 +15,8 @@ struct ReconstructBusses : public ScriptPass {
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log_error("No design object");
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log_error("No design object");
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return;
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return;
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}
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}
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log("Running reconstructbusses pass\n");
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log_flush();
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for (auto module : design->modules()) {
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for (auto module : design->modules()) {
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// Collect all wires with a common prefix
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// Collect all wires with a common prefix
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dict<std::string, std::vector<RTLIL::Wire *>> wire_groups;
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dict<std::string, std::vector<RTLIL::Wire *>> wire_groups;
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@ -47,7 +49,8 @@ struct ReconstructBusses : public ScriptPass {
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wire_groups[no_bitblast_prefix].push_back(wire);
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wire_groups[no_bitblast_prefix].push_back(wire);
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}
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}
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}
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}
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std::map<std::string, RTLIL::Wire *> wirenames_to_remove;
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pool<RTLIL::Wire *> wires_to_remove;
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// Reconstruct vectors
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// Reconstruct vectors
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for (auto &it : wire_groups) {
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for (auto &it : wire_groups) {
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std::string prefix = it.first;
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std::string prefix = it.first;
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@ -83,100 +86,103 @@ struct ReconstructBusses : public ScriptPass {
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new_wire->port_output = 1;
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new_wire->port_output = 1;
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break;
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break;
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}
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}
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RTLIL::SigSpec new_wire_s(new_wire);
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// Reconnect cells
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections_) {
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RTLIL::SigSpec new_sig;
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bool modified = false;
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for (auto chunk : conn.second.chunks()) {
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// std::cout << "Port:" << conn.first.c_str() << std::endl;
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// std::cout << "Conn:" << chunk.wire->name.c_str() << std::endl;
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// Find the connections that match the wire group prefix
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if (chunk.wire->name.begins_with((prefix + "_").c_str())) {
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std::string ch_name = chunk.wire->name.c_str();
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std::string::iterator ch_end = ch_name.end() - 1;
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if ((*ch_end) == '_') {
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ch_name = ch_name.substr(0, ch_name.size() - 1);
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std::string ch_index_str = ch_name.substr(ch_name.find_last_of('_') + 1);
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// std::cout << "ch_name: " << ch_name << std::endl;
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if (!ch_index_str.empty()) {
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// Create a new connection sigspec that matches the previous bit index
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int ch_index = std::stoi(ch_index_str);
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RTLIL::SigSpec bit = RTLIL::SigSpec(new_wire, ch_index, 1);
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new_sig.append(bit);
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modified = true;
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}
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}
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} else {
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new_sig.append(chunk);
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modified = true;
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}
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}
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// Replace the previous connection
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if (modified)
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conn.second = new_sig;
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}
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}
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// Reconnect top connections before removing the old wires
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for (auto wire : wires) {
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for (auto wire : wires) {
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std::string wire_name = wire->name.c_str();
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std::string wire_name = wire->name.c_str();
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// std::cout << "Wire to remove: " << wire_name << std::endl;
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wirenames_to_remove.emplace(wire_name, new_wire);
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for (auto &conn : module->connections()) {
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RTLIL::SigSpec lhs = conn.first;
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RTLIL::SigSpec rhs = conn.second;
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auto lit = lhs.chunks().rbegin();
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if (lit == lhs.chunks().rend())
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continue;
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auto rit = rhs.chunks().rbegin();
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if (rit == rhs.chunks().rend())
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continue;
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RTLIL::SigChunk sub_rhs = *rit;
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while (lit != lhs.chunks().rend()) {
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RTLIL::SigChunk sub_lhs = *lit;
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std::string conn_lhs = sub_lhs.wire->name.c_str();
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std::string conn_rhs = sub_rhs.wire->name.c_str();
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// The connection LHS matches a wire that is replaced by a bus
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// std::cout << "Conn: " << conn_lhs << " to: " << conn_rhs << std::endl;
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if (wire_name == conn_lhs) {
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std::string::iterator conn_lhs_end = conn_lhs.end() - 1;
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if ((*conn_lhs_end) == '_') {
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conn_lhs = conn_lhs.substr(0, conn_lhs.size() - 1);
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std::string ch_index_str = conn_lhs.substr(conn_lhs.find_last_of('_') + 1);
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if (!ch_index_str.empty()) {
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// std::cout << "Conn LHS: " << conn_lhs << std::endl;
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// std::string conn_rhs = sub_rhs.wire->name.c_str();
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// std::cout << "Conn RHS: " << conn_rhs << std::endl;
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int ch_index = std::stoi(ch_index_str);
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// Create the LHS sigspec of the desired bit
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RTLIL::SigSpec bit = RTLIL::SigSpec(new_wire, ch_index, 1);
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if (sub_rhs.size() > 1) {
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// If RHS has width > 1, replace with the bitblasted RHS corresponding to the connected bit
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RTLIL::SigSpec rhs_bit =
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RTLIL::SigSpec(sub_rhs.wire, ch_index, 1);
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// And connect it
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module->connect(bit, rhs_bit);
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} else {
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// Else, directly connect
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module->connect(bit, sub_rhs);
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}
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}
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}
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}
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lit++;
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if (++rit != rhs.chunks().rend())
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rit++;
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}
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}
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}
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// Remove old wires
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pool<RTLIL::Wire *> wires_to_remove;
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for (auto wire : wires) {
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wires_to_remove.insert(wire);
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wires_to_remove.insert(wire);
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}
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}
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module->remove(wires_to_remove);
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}
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}
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// Reconnect cells
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections_) {
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RTLIL::SigSpec new_sig;
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bool modified = false;
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for (auto chunk : conn.second.chunks()) {
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// std::cout << "Port:" << conn.first.c_str() << std::endl;
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// std::cout << "Conn:" << chunk.wire->name.c_str() << std::endl;
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// Find the connections that match the wire group prefix
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std::string lhs_name = chunk.wire->name.c_str();
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std::map<std::string, RTLIL::Wire *>::iterator itr = wirenames_to_remove.find(lhs_name);
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if (itr != wirenames_to_remove.end()) {
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std::string ch_name = chunk.wire->name.c_str();
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std::string::iterator ch_end = ch_name.end() - 1;
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if ((*ch_end) == '_') {
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ch_name = ch_name.substr(0, ch_name.size() - 1);
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std::string ch_index_str = ch_name.substr(ch_name.find_last_of('_') + 1);
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// std::cout << "ch_name: " << ch_name << std::endl;
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if (!ch_index_str.empty()) {
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// Create a new connection sigspec that matches the previous bit index
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int ch_index = std::stoi(ch_index_str);
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RTLIL::SigSpec bit = RTLIL::SigSpec(itr->second, ch_index, 1);
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new_sig.append(bit);
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modified = true;
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}
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}
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} else {
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new_sig.append(chunk);
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modified = true;
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}
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}
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// Replace the previous connection
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if (modified)
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conn.second = new_sig;
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}
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}
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// Reconnect top connections before removing the old wires
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// std::cout << "Wire to remove: " << wire_name << std::endl;
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for (auto &conn : module->connections()) {
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RTLIL::SigSpec lhs = conn.first;
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RTLIL::SigSpec rhs = conn.second;
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auto lit = lhs.chunks().rbegin();
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if (lit == lhs.chunks().rend())
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continue;
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auto rit = rhs.chunks().rbegin();
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if (rit == rhs.chunks().rend())
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continue;
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RTLIL::SigChunk sub_rhs = *rit;
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while (lit != lhs.chunks().rend()) {
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RTLIL::SigChunk sub_lhs = *lit;
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std::string conn_lhs = sub_lhs.wire->name.c_str();
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std::string conn_rhs = sub_rhs.wire->name.c_str();
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// The connection LHS matches a wire that is replaced by a bus
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// std::cout << "Conn: " << conn_lhs << " to: " << conn_rhs << std::endl;
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std::map<std::string, RTLIL::Wire *>::iterator itr = wirenames_to_remove.find(conn_lhs);
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if (itr != wirenames_to_remove.end()) {
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std::string::iterator conn_lhs_end = conn_lhs.end() - 1;
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if ((*conn_lhs_end) == '_') {
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conn_lhs = conn_lhs.substr(0, conn_lhs.size() - 1);
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std::string ch_index_str = conn_lhs.substr(conn_lhs.find_last_of('_') + 1);
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if (!ch_index_str.empty()) {
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// std::cout << "Conn LHS: " << conn_lhs << std::endl;
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// std::string conn_rhs = sub_rhs.wire->name.c_str();
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// std::cout << "Conn RHS: " << conn_rhs << std::endl;
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int ch_index = std::stoi(ch_index_str);
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// Create the LHS sigspec of the desired bit
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RTLIL::SigSpec bit = RTLIL::SigSpec(itr->second, ch_index, 1);
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if (sub_rhs.size() > 1) {
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// If RHS has width > 1, replace with the bitblasted RHS corresponding to the
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// connected bit
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RTLIL::SigSpec rhs_bit = RTLIL::SigSpec(sub_rhs.wire, ch_index, 1);
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// And connect it
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module->connect(bit, rhs_bit);
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} else {
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// Else, directly connect
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module->connect(bit, sub_rhs);
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}
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}
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}
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}
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lit++;
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if (++rit != rhs.chunks().rend())
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rit++;
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}
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}
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// Remove old wires
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module->remove(wires_to_remove);
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// Update module port list
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// Update module port list
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module->fixup_ports();
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module->fixup_ports();
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}
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}
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