mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-10 03:31:26 +00:00
Code Activity

memory_libmap: Fix use of uninitialized value for async read ports

Browse source 
The code in memory_libmap expects `clk_en` to be initialized for all
`PortVariant`s but the parsing in memlib.cc didn't initialize it for
variants of kind `PortKind::Ar` (async read ports).

While this fixes the immediate CI failure, it would be best to refactor
the code so it becomes obvious if something isn't initialized.
This commit is contained in:
Jannis Harder 2025-09-09 13:24:48 +02:00
parent 23e4c0e424
commit 61a00b9131
1 changed files with 3 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/memory/memlib.cc
View file

@ -855,7 +855,9 @@ struct Parser {
PortVariant var;
var.options = portopts;
var.kind = pdef.kind;
if (pdef.kind != PortKind::Ar) {
if (pdef.kind == PortKind::Ar) {
var.clk_en = false;
} else {
const ClockDef *cdef = find_single_cap(pdef.clock, cram.options, portopts, "clock");
if (!cdef)
log_error("%s:%d: missing clock capability.\n", filename.c_str(), orig_line);