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Merge branch 'master' of github.com:cliffordwolf/yosys

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This commit is contained in:
Clifford Wolf 2013-07-09 19:00:10 +02:00
commit 618b2ac994
5 changed files with 189 additions and 37 deletions
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18
tests/simple/signedexpr.v Normal file
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@ -0,0 +1,18 @@
module test01(a, b, xu, xs, yu, ys, zu, zs);
input signed [1:0] a;
input signed [2:0] b;
output [3:0] xu, xs;
output [3:0] yu, ys;
output zu, zs;
assign xu = (a + b) + 3'd0;
assign xs = (a + b) + 3'sd0;
assign yu = {a + b} + 3'd0;
assign ys = {a + b} + 3'sd0;
assign zu = a + b != 3'd0;
assign zs = a + b != 3'sd0;
endmodule

4
tests/tools/autotest.sh
View file

@ -51,7 +51,7 @@ create_ref() {
(
set +x
prefix="$2"
xilver=$( ls -v /opt/Xilinx/ | tail -n1; )
xilver=$( ls -v /opt/Xilinx/ | grep '^[0-9]' | tail -n1; )
case "$( uname -m )" in
x86_64)
set --; . /opt/Xilinx/$xilver/ISE_DS/settings64.sh ;;
@ -73,7 +73,7 @@ compile_and_run() {
(
set +x
files=( "$@" )
xilver=$( ls -v /opt/Xilinx/ | tail -n1; )
xilver=$( ls -v /opt/Xilinx/ | grep '^[0-9]' | tail -n1; )
case "$( uname -m )" in
x86_64)
set --; . /opt/Xilinx/$xilver/ISE_DS/settings64.sh ;;