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Add PRIM_HDL_ASSERTION support to Verific importer

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-04-07 18:38:42 +02:00
parent 0ac768f9df
commit 617c60cea6
1 changed files with 19 additions and 3 deletions
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22
frontends/verific/verific.cc
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@ -1258,11 +1258,27 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
continue; continue;
} }
if (inst->Type() == PRIM_HDL_ASSERTION)
{
SigBit cond = net_map_at(inst->GetInput());
if (verific_verbose)
log(" assert condition %s.\n", log_signal(cond));
const char *assume_attr = nullptr; // inst->GetAttValue("assume");
Cell *cell = nullptr;
if (assume_attr != nullptr && !strcmp(assume_attr, "1"))
cell = module->addAssume(NEW_ID, cond, State::S1);
else
cell = module->addAssert(NEW_ID, cond, State::S1);
import_attributes(cell->attributes, inst);
continue;
}
if (inst->IsPrimitive()) if (inst->IsPrimitive())
{ {
if (inst->Type() == PRIM_HDL_ASSERTION)
continue;
if (!mode_keep) if (!mode_keep)
log_error("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name()); log_error("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name());