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Progress in examples/gowin/

This commit is contained in:
Clifford Wolf 2016-11-08 19:07:22 +01:00
parent e9d73d2ee0
commit 617693e691
5 changed files with 95 additions and 21 deletions

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@ -3,3 +3,10 @@ set -ex
yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v
$GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW2A55-PBGA484-6 \
-warning_all -out demo_out.v -rpt demo.rpt -tr demo_tr.html -bit demo.bit
# post place&route simulation (icarus verilog)
if false; then
iverilog -D POST_IMPL -o testbench -s testbench testbench.v \
demo_out.v $(yosys-config --datdir/gowin/cells_sim.v)
vvp -N testbench
fi