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Do not run xilinx_srl_pm in fixed loop

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This commit is contained in:
Eddie Hung 2019-08-22 10:51:04 -07:00
parent 7188972645
commit 61639d5387
1 changed files with 24 additions and 28 deletions
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18
passes/pmgen/xilinx_srl.cc
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@ -202,22 +202,18 @@ struct XilinxSrlPass : public Pass {
log_cmd_error("'-fixed' and/or '-variable' must be specified.\n"); log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
for (auto module : design->selected_modules()) { for (auto module : design->selected_modules()) {
bool did_something = false;
if (fixed)
do {
auto pm = xilinx_srl_pm(module, module->selected_cells()); auto pm = xilinx_srl_pm(module, module->selected_cells());
pm.ud_fixed.minlen = minlen; pm.ud_fixed.minlen = minlen;
if (fixed) {
// TODO: How to get these automatically? // TODO: How to get these automatically?
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
did_something = pm.run_fixed(run_fixed); pm.run_fixed(run_fixed);
} while (did_something); }
if (variable) if (variable) {
do {
auto pm = xilinx_srl_pm(module, module->selected_cells());
pm.ud_variable.minlen = minlen;
// Since `nusers` does not count module ports as a user, // Since `nusers` does not count module ports as a user,
// and since `sigmap` does not always make such ports // and since `sigmap` does not always make such ports
// the canonical signal.. need to maintain a pool these // the canonical signal.. need to maintain a pool these
@ -228,8 +224,8 @@ struct XilinxSrlPass : public Pass {
for (auto b : pm.sigmap(w)) for (auto b : pm.sigmap(w))
pm.ud_variable.output_bits.insert(b); pm.ud_variable.output_bits.insert(b);
} }
did_something = pm.run_variable(run_variable); pm.run_variable(run_variable);
} while (did_something); }
} }
} }
} XilinxSrlPass; } XilinxSrlPass;