mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Merge remote-tracking branch 'origin/xaig' into xc7mux

Browse source
This commit is contained in:
Eddie Hung 2019-06-26 10:33:54 -07:00
commit 612083a807
4 changed files with 67 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

12
techlibs/ecp5/abc_5g_nowide.lut Normal file
View file

@ -0,0 +1,12 @@
# ECP5-5G LUT library for ABC
# Note that ECP5 architecture assigns difference
# in LUT input delay to interconnect, so this is
# considered too
# Simple LUTs
# area D C B A
1 1 141
2 1 141 275
3 1 141 275 379
4 1 141 275 379 379

16
techlibs/ecp5/synth_ecp5.cc
View file

@ -76,7 +76,7 @@ struct SynthEcp5Pass : public ScriptPass
log(" -nodram\n");
log(" do not use distributed RAM cells in output netlist\n");
log("\n");
log(" -nomux\n");
log(" -nowidelut\n");
log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
log("\n");
log(" -abc2\n");
@ -96,7 +96,7 @@ struct SynthEcp5Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file;
bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, abc9, vpr;
bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
void clear_flags() YS_OVERRIDE
{
@ -108,7 +108,7 @@ struct SynthEcp5Pass : public ScriptPass
nodffe = false;
nobram = false;
nodram = false;
nomux = false;
nowidelut = false;
flatten = true;
retime = false;
abc2 = false;
@ -176,8 +176,8 @@ struct SynthEcp5Pass : public ScriptPass
nodram = true;
continue;
}
if (args[argidx] == "-nomux") {
nomux = true;
if (args[argidx] == "-nowidelut" || args[argidx] == "-nomux") {
nowidelut = true;
continue;
}
if (args[argidx] == "-abc2") {
@ -273,14 +273,16 @@ struct SynthEcp5Pass : public ScriptPass
}
run("techmap -map +/ecp5/latches_map.v");
if (abc9) {
if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else
run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
} else {
if (nomux)
if (nowidelut)
run("abc -lut 4 -dress");
else
run("abc -lut 4:7 -dress");
}
run("clean");
}

10
techlibs/xilinx/abc_xc7_nowide.lut Normal file
View file

@ -0,0 +1,10 @@
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf
# and https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json
# K area delay
1 1 127
2 2 127 238
3 3 127 238 407
4 3 127 238 407 472
5 3 127 238 407 472 631
6 5 127 238 407 472 631 642

44
techlibs/xilinx/synth_xilinx.cc
View file

@ -73,6 +73,12 @@ struct SynthXilinxPass : public ScriptPass
log(" -nosrl\n");
log(" disable inference of shift registers\n");
log("\n");
log(" -nocarry\n");
log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
log("\n");
log(" -nowidelut\n");
log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
log("\n");
log(" -widemux <int>\n");
log(" enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
log(" above this number of inputs (minimum value 5).\n");
@ -99,7 +105,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, abc, arch;
bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
int widemux;
void clear_flags() YS_OVERRIDE
@ -107,7 +113,7 @@ struct SynthXilinxPass : public ScriptPass
top_opt = "-auto-top";
edif_file.clear();
blif_file.clear();
abc = "abc";
arch = "xc7";
flatten = false;
retime = false;
vpr = false;
@ -115,7 +121,9 @@ struct SynthXilinxPass : public ScriptPass
nobram = false;
nodram = false;
nosrl = false;
arch = "xc7";
nocarry = false;
nowidelut = false;
abc9 = false;
widemux = 0;
}
@ -159,6 +167,14 @@ struct SynthXilinxPass : public ScriptPass
retime = true;
continue;
}
if (args[argidx] == "-nocarry") {
nocarry = true;
continue;
}
if (args[argidx] == "-nowidelut") {
nowidelut = true;
continue;
}
if (args[argidx] == "-vpr") {
vpr = true;
continue;
@ -184,7 +200,7 @@ struct SynthXilinxPass : public ScriptPass
continue;
}
if (args[argidx] == "-abc9") {
abc = "abc9";
abc9 = true;
continue;
}
break;
@ -321,7 +337,7 @@ struct SynthXilinxPass : public ScriptPass
techmap_args += " -map +/xilinx/arith_map.v";
if (vpr)
techmap_args += " -D _EXPLICIT_CARRY";
else if (abc == "abc9")
else if (abc9)
techmap_args += " -D _CLB_CARRY";
}
run("techmap " + techmap_args);
@ -338,12 +354,20 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_luts")) {
run("opt_expr -mux_undef");
if (abc == "abc9")
run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
else if (help_mode)
run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
else if (abc9) {
if (nowidelut)
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
else
run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
}
else {
if (nowidelut)
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
else
run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
}
run("clean");
// This shregmap call infers fixed length shift registers after abc